# Power supply
Source: [https://docs.qualcomm.com/doc/80-WL740-3/topic/power-supply.html](https://docs.qualcomm.com/doc/80-WL740-3/topic/power-supply.html)
For the layout and routing of the power supply, the following guidelines are
recommended:
- Isolate digital and analog power supplies. If the user is designing a module, it's
recommended to have two separate power supplies for the stamp holes. If the user
adopts CoB, it's recommended to merge digital and analog power supplies at a distant
point.
- When connecting power traces from analog or digital power to the power pins of each
chip, it's recommended to use a star connection to prevent mutual interference
between the power pins.
- Place bypass capacitors for power pins and capacitors for circuit stabilization near
the power pins of the chip.
- Capacitors connected in parallel to the power pins should have their ground pads
connected to the main GND through nearby vias.
- The width of the power traces can be calculated based on the design reference
current.
Note: The design reference current of each power supply pin listed in
the following table is the maximum current value of the pin and is used to guide
customers in calculating PCB trace width. In actual applications, the current of this
pin won't exceed the values listed in the table.
Table : QCC743 power pin description
| Pin number | Name | Typical value | Direction | Function description | Design reference current |
| --- | --- | --- | --- | --- | --- |
| 2 | AVDD33\_RF1 | 3.3 V | IN | PA | 500 mA |
| 3 | AVDD33\_RF2 | 3.3 V | IN | TMX | 50 mA |
| 8 | VDDIO1 | 3.3 V or 1.8 V | IN | GPIO-0, 1, 2, 3, 10, 11, 12, 13,14,15 | 160 mA |
| 18 | AVDD33\_AON | 3.3 V | IN | GPIO-16, 17 | 82 mA |
| 19 | VDD18\_Flash | 1.8 V | — | Power pin; generate from internal LDO (3.3 V IN); need decoup cap;
for internal Flash | — |
| 20 | PVDD33\_DCDC | 3.3 V | IN | DCDC input power | 236 mA |
| 21 | SW\_DCDC | | — | Switch DCDC; connect 2.2 μH | — |
| 22 | DCDC\_OUT | 1.8 V | OUT | DCDC\_OUT, typical = 1.8 V | 200 mA |
| 23 | DVDD11 | 1.1 V | — | Power pin; need decoup cap; generate from internal LDO (DCDC\_OUT =
1.8 V IN) | — |
| 24 | VDDIO\_IO | 3.3 V | IN | Input pin | 50 mA |
| 30 | VDDIO2 | 3.3 V or 1.8 V | IN | GPIO-20, 21, 22, 27, 28, 29, 30 | 250 mA |
| 37 | AVDD33\_RF3 | 3.3 V | IN | Input pin; for analog xtal | 50 mA |
| 38 | AVDD18\_RF | 1.8 V | IN | Input pin; from DCDC\_OUT = 1.8 V; for CLKPLL | 50 mA |
| 39 | AVDD15\_RF2 | 1.5 V | — | Power pin; generate from internal LDO (DCDC\_OUT = 1.8 V IN); need
decoup cap for analog RBB, LO | — |
| 40 | AVDD15\_RF1 | 1.5 V | — | Power pin; generate from internal LDO (DCDC\_OUT = 1.8 V IN); need
decoup cap for analog LNA | — |
Table : QCC744 power pin description
| Pin number | Name | Typical value | Direction | Function description | Design reference current |
| --- | --- | --- | --- | --- | --- |
| 2 | AVDD33\_RF1 | 3.3 V | IN | PA power | 500 mA |
| 3 | AVDD33\_RF2 | 3.3 V | IN | TMX power | 50 mA |
| 13 | VDDIO1 | 3.3 V or 1.8 V | IN | GPIO-0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13,14, 15 | 256 mA |
| 26 | AVDD33\_AON | 3.3 V | IN | AON power, GPIO-16,17,18,19 | 114 mA |
| 27 | VDD18\_Flash | 1.8 V | — | Power pin; generate from internal LDO (3.3V IN); need decoup cap; for
internal PSRAM | — |
| 28 | PVDD33\_DCDC | 3.3 V | IN | DCDC input power | 236 mA |
| 29 | SW\_DCDC | | — | Switch DCDC; connect 2.2 μH | — |
| 30 | DCDC\_OUT | 1.8 V | OUT | DCDC\_OUT; typical=1.8 V | 200 mA |
| 31 | DVDD11 | 1.1 V | — | Power pin; need decoup cap; generate from internal LDO
(DCDC\_OUT=1.8 V IN); for SoC | — |
| 32 | VDDIO\_IO | 3.3 V | IN | Input pin | — |
| 42 | VDDIO2 | 3.3 V or 1.8 V | IN | GPIO-20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,
34 | 240 mA |
| 53 | AVDD33\_RF3 | 3.3 V | IN | Input pin; for analog xtal | 50 mA |
| 54 | AVDD18\_RF | 1.8 V | IN | Input pin; from DCDC\_OUT=1.8 V; for CLKPLL | 50 mA |
| 55 | AVDD15\_RF2 | 1.5 V | — | Power pin; generate from internal LDO (DCDC\_OUT=1.8 V IN); need
decoup cap for analog RBB, LO | — |
| 56 | AVDD15\_RF1 | 1.5 V | — | Power pin; generate from internal LDO (DCDC\_OUT=1.8 V IN); need
decoup cap for analog LNA | — |
Table : QCC748 power pin description
| Pin number | Name | Typical value | Direction | Function description | Design reference current |
| --- | --- | --- | --- | --- | --- |
| 2 | AVDD33\_RF1 | 3.3 V | IN | PA power | 500 mA |
| 3 | AVDD33\_RF2 | 3.3 V | IN | TMX power | 50 mA |
| 13 | VDDIO1 | 3.3 V or 1.8 V | IN | GPIO-0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13,14, 15 | 256 mA |
| 26 | AVDD33\_AON | 3.3 V | IN | AON power, GPIO-16,17,18,19 | 114 mA |
| 27 | VDD18\_Flash | 1.8 V | — | Power pin; generate from internal LDO (3.3V IN); need decoup cap; for
internal PSRAM | — |
| 28 | PVDD33\_DCDC | 3.3 V | IN | DCDC input power | 236 mA |
| 29 | SW\_DCDC | | — | Switch DCDC; connect 2.2 μH | — |
| 30 | DCDC\_OUT | 1.8 V | OUT | DCDC\_OUT; typical=1.8 V | 200 mA |
| 31 | DVDD11 | 1.1 V | — | Power pin; need decoup cap; generate from internal LDO
(DCDC\_OUT=1.8 V IN); for SoC | — |
| 32 | VDDIO\_USB | 3.3 V | IN | Input pin; for USB power | — |
| 42 | VDDIO2 | 3.3 V or 1.8 V | IN | GPIO-20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,
34 | 240 mA |
| 53 | AVDD33\_RF3 | 3.3 V | IN | Input pin; for analog xtal | 50 mA |
| 54 | AVDD18\_RF | 1.8 V | IN | Input pin; from DCDC\_OUT=1.8 V; for CLKPLL | 50 mA |
| 55 | AVDD15\_RF2 | 1.5 V | — | Power pin; generate from internal LDO (DCDC\_OUT=1.8 V IN); need
decoup cap for analog RBB, LO | — |
| 56 | AVDD15\_RF1 | 1.5 V | — | Power pin; generate from internal LDO (DCDC\_OUT=1.8 V IN); need
decoup cap for analog LNA | — |
The analog power traces in the PCB use a star routing method, as shown below:
Figure : Analog power PCB traces
The digital power traces in the PCB are separate from the analog power, as shown
below:
Figure : Digital power PCB traces
For the DCDC power section, note that the ground pad of the capacitor connected in
parallel with DCDC\_OUT (device circled in [Figure : DCDC power PCB traces](https://docs.qualcomm.com/doc/80-WL740-3/topic/power-supply.html#power-supply__fig_ih1_hm5_11c)) has a short
return path to the chip’s EPAD. The DCDC power traces are shown below:
Figure : DCDC power PCB traces
Last Published: Apr 08, 2025
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