# GPIO
Source: [https://docs.qualcomm.com/doc/80-WL740-8/topic/gpio.html](https://docs.qualcomm.com/doc/80-WL740-8/topic/gpio.html)
## External
Flash
Source: [https://docs.qualcomm.com/doc/80-WL740-8/topic/gpio.html](https://docs.qualcomm.com/doc/80-WL740-8/topic/gpio.html)
QCC743-1/QCC744-1 do not have internal Flash by default. If the customer designs with the
QCC743-1/QCC744-1, external Flash is required. The connection reference for Flash is shown in
the following schematic design:
- GPIOxF: connect to QCC74x
- GPIOx: connect to the module stamp hole
Table : Schematic for external Flash
| QCC743-1 |  |
| --- | --- |
| QCC744-1 |  |
## GPIO precautions for low-power
applications
Source: [https://docs.qualcomm.com/doc/80-WL740-8/topic/gpio.html](https://docs.qualcomm.com/doc/80-WL740-8/topic/gpio.html)
### Power wake-up mode
Source: [https://docs.qualcomm.com/doc/80-WL740-8/topic/gpio.html](https://docs.qualcomm.com/doc/80-WL740-8/topic/gpio.html)
QCC74x has flexible low-power modes including HBN 0/1/2 and PDS
1/2/3/7/15.
- HBN 0~2
- HBN 2: support AON GPIO wake-up
- HBN 1: HBN 2 + RTC
- HBN 0: HBN 1 + 4KB HBN\_RAM + ACOMP
- PDS 1~15
- PDS 1/2/3/7/15 power domain is shown as below table.
Table : Power mode
| Scenario | PD\_AON | PD\_AON\_HBNRTC | PD\_AON
\_HBNCORE | PD\_CORE | PD\_CORE
\_MISC | PD\_FERI | PD\_CPU | PD\_WB |
| :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: |
| Normal | ON | ON | ON | ON | ON | ON | ON | ON |
| PDS 1 | ON | ON | ON | ON | ON | ON | ON | OFF |
| PDS 2 | ON | ON | ON | ON | ON | ON | OFF | ON |
| PDS 3 | ON | ON | ON | ON | ON | ON | OFF | OFF |
| PDS 7 | ON | ON | ON | ON | ON | OFF | OFF | OFF |
| PDS 15 | ON | ON | ON | ON | OFF | OFF | OFF | OFF |
| HBN 0 | ON | ON | ON | OFF | OFF | OFF | OFF | OFF |
| HBN 1 | ON | ON | OFF | OFF | OFF | OFF | OFF | OFF |
| HBN 2 | ON | OFF | OFF | OFF | OFF | OFF | OFF | OFF |
### GPIO type
Source: [https://docs.qualcomm.com/doc/80-WL740-8/topic/gpio.html](https://docs.qualcomm.com/doc/80-WL740-8/topic/gpio.html)
### AON\_IO controller
AON\_IO controller controls AON\_IO (GPIO16/17/18/19) with reg\_en\_aon\_ctrl\_gpio=1 in all
power modes (normal mode, HBN 0/1/2, PDS 1/2/3/7/15).
Input enable (IE), Pull-up (PU) and Pull-down (PD) functions of AON\_IO can be configured
independently at any power states.
### GLB\_IO controller
GLB\_IO controller controls all GPIO (GPIO0~34, including AON\_IO with reg\_en\_aon\_ctrl\_GPIO =
0) in normal mode and PDS 1/2/3/7 low-power mode.
The IE, PU, and PD configurations of GLB\_IO can be independently configured in normal mode
and PDS 1/2/3/7 power states.
### PDS\_IO controller
PDS\_IO controller controls all I/Os excluding AON\_IO, including GPIO0~15 and GPIO20~34. It
is active in PDS 15 mode.
The IE, PU, and PD configurations of PDS\_IO must be grouped together. The configurations
are as follows:
GPIO0~15 share one group of PU/PD/IE configurations. For example, if GPIO0 is configured as
input pull-down, then GPIO0~15 will all be configured as input pull-down.
GPIO20~34 share one group of PU/PD/IE configurations. For example, if GPIO29 is configured
as input pull-up, then GPIO20~34 will all be configured as input pull-up.
### GPIO wake-up mode
Source: [https://docs.qualcomm.com/doc/80-WL740-8/topic/gpio.html](https://docs.qualcomm.com/doc/80-WL740-8/topic/gpio.html)
AON\_IO (GPIO16~19) supports wake-up in PDS 1~15 and HBN 0~2 power modes. It supports
wake-up triggers of falling edge, rising edge, both edges, high level, and low level.
GPIO0~15 and GPIO20~34 support wake-up in PDS 1~15 power modes, but only support
triggers of falling edge, high level, and rising edge. When using the rising edge trigger, the
default state must be low level.
Each group of GPIO0~7, GPIO8~15, GPIO16~19, GPIO20~27, and GPIO28~34 share the same
wake-up trigger mode. For example, the wake-up mode of GPIO0 and GPIO7 must be the same, the
wake-up mode of GPIO0 and GPIO8 can be different, and the wake-up mode of GPIO20 and GPIO27
must be the same.
### GPIO leakage
Source: [https://docs.qualcomm.com/doc/80-WL740-8/topic/gpio.html](https://docs.qualcomm.com/doc/80-WL740-8/topic/gpio.html)
Figure : Circuit diagram of GPIO
When IE=1, the GPIO operates in input mode. When OE=1, the GPIO operates in output mode.
When PU=1, the GPIO pin is pulled up to 3.3 V through a pull-up resistor of dozens of kΩ.
When PD=1, the GPIO pin is pulled down to the ground through a pull-down resistor of dozens of
kΩ.
| Input Enable of GPIO | GPIO pin levels | Leakage occurrence |
| --- | --- | --- |
| 0 | High (internal pull-up or external pull-up or other peripheral input high
level) | No leakage |
| 0 | Low (internal pull-down or external pull-down or other peripheral input low
level) | No leakage |
| 0 | Analog signal (for example, 1.6 V) | No leakage |
| 0 | Pin floating, no pull-up/pull-down, no other peripheral input signals | No leakage |
| 1 | High (internal pull-up or external pull-up or other peripheral input high
level) | No leakage |
| 1 | Low (internal pull-down or external pull-down or other peripheral input low
level) | No leakage |
| 1 | Analog signal (for example, 1.6 V) | Leakage |
| 1 | Pin floating, no pull-up/pull-down, no other peripheral input signals | Leakage |
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When the internal pull-up/pull-down configuration of an I/O is inconsistent with the external
pull-up/pull-down configuration, the voltage on the I/O pin can be in an intermediate state,
which can result in leakage. For example, if there is an external pull-up on any pin of the
GPIO0~15 group, the entire GPIO0~15 group should not be configured as an internal pull-down,
as it can cause leakage.
### Wake-up pin selection
Source: [https://docs.qualcomm.com/doc/80-WL740-8/topic/gpio.html](https://docs.qualcomm.com/doc/80-WL740-8/topic/gpio.html)
In PDS 15 mode, all pins in the GPIO0~15 and GPIO20~34 groups should have a
deterministic high or low-level input (via PCB pull-up or pull-down resistors), unless this
group has no wake-up source, in which case IE can be set to 0.
In PDS 15 mode, it is generally not recommended to use the built-in pull-up/pull-down
of the GPIO to prevent leakage, as the pull-up/pull-down settings apply to the GPIO0~15
(GPIO20~34) group, and it is difficult to ensure that all pins within this group can be
configured as pull-up or pull-down since different I/O interface requires different pull
options. It is recommended to use PCB pull-up/pull-down resistors instead.
I/O Hold: I/O Hold is not supported in PDS 15 mode. If I/O Hold
is required, it can be implemented using external pull-up/pull-down
resistors.
In low-power applications, if there are ADC input I/O and wake-up source I/O in the
group GPIO0~15. Since IE=1 is in this group, the analog input of the ADC causes leakage, and
other GPIOs must be used to control a MOSFET to isolate the input of the ADC. The same applies
to GPIO20~34.
### Electrical timing requirements for GPIO wake-up
Source: [https://docs.qualcomm.com/doc/80-WL740-8/topic/gpio.html](https://docs.qualcomm.com/doc/80-WL740-8/topic/gpio.html)
I/O wake-up timing requirements
- PDS I/O: 100 μs
- AON I/O: 100 μs
- ACOMP: 50 μs
Note: The customer must determine which GPIO triggers the falling edge
wake-up event and the low level must be held for at least 2 ms after the falling
edge.
For example, if GPIO0 is used as the pds\_io wake-up pin with a falling edge trigger,
the level timing must satisfy the requirement of holding a low level for at least 100 µs
after the falling edge. To confirm the GPIO number, it is required to hold a low level
for at least 2 ms after the falling edge.
If GPIO18 is used as the aon\_io wake-up pin with a high-level trigger, the level timing
must satisfy the requirement of holding a high level for at least 100 µs.
If GPIO13 is used as the ACOMP wake-up pin with a rising edge trigger, the level timing
must satisfy the requirement of holding a high level for at least 50 µs after the rising
edge.
### GPIO wake-up configuration
template
Source: [https://docs.qualcomm.com/doc/80-WL740-8/topic/gpio.html](https://docs.qualcomm.com/doc/80-WL740-8/topic/gpio.html)
### Pull-up resistor recommendations for typical applications
Source: [https://docs.qualcomm.com/doc/80-WL740-8/topic/gpio.html](https://docs.qualcomm.com/doc/80-WL740-8/topic/gpio.html)
- I2C: Suggested PCB pull-up resistors of 4.7K~10K.
- Flash SPI: Suggested PCB pull-up resistor of 10K.
- SDIO: Suggested PCB pull-up resistor of 100K.
- UART: Suggested PCB pull-up resistor of
10K.
### GPIO wake-up configuration template for low-power applications
| GPIO | Chip external PU/PD | Function | Wake-up method | Note | IE/PU/PD settings during sleep |
| --- | --- | --- | --- | --- | --- |
| GPIO0 (ADC9) | | | | For PDS I/O, the wake-up mode must be the same. | IE=0, PU=0, PD=0 |
| GPIO1 (ADC8) | | | | For PDS I/O, the wake-up mode must be the same. | IE=0, PU=0, PD=0 |
| GPIO2 (ACOMP/ADC2/Boot) | | | | For PDS I/O, the wake-up mode must be the same. | IE=0, PU=0, PD=0 |
| GPIO3 (ACOMP/ADC3) | | | | For PDS I/O, the wake-up mode must be the same. | IE=0, PU=0, PD=0 |
| GPIO4 | | | | For PDS I/O, the wake-up mode must be the same. | IE=0, PU=0, PD=0 |
| GPIO5 | | | | For PDS I/O, the wake-up mode must be the same. | IE=0, PU=0, PD=0 |
| GPIO6 | | | | For PDS I/O, the wake-up mode must be the same. | IE=0, PU=0, PD=0 |
| GPIO7 | | | | For PDS I/O, the wake-up mode must be the same. | IE=0, PU=0, PD=0 |
| GPIO8 | | | | For PDS I/O, the wake-up mode must be the same. | IE=0, PU=0, PD=0 |
| GPIO9 | | | | For PDS I/O, the wake-up mode must be the same. | IE=0, PU=0, PD=0 |
| GPIO10 (ACOMP/ADC7) | | | | For PDS I/O, the wake-up mode must be the same. | IE=0, PU=0, PD=0 |
| GPIO11 | | | | For PDS I/O, the wake-up mode must be the same. | IE=0, PU=0, PD=0 |
| GPIO12 (ACOMP/ADC6) | | | | For PDS I/O, the wake-up mode must be the same. | IE=0, PU=0, PD=0 |
| GPIO13 (ACOMP/ADC5) | | | | For PDS I/O, the wake-up mode must be the same. | IE=0, PU=0, PD=0 |
| GPIO14 (ACOMP/ADC4) | | | | For PDS I/O, the wake-up mode must be the same. | IE=0, PU=0, PD=0 |
| GPIO15 | | | | For PDS I/O, the wake-up mode must be the same. | IE=0, PU=0, PD=0 |
| GPIO16 (XTAL32K) | | | | For AON I/O, the wake-up mode must be the same. | IE=0, PU=0, PD=0 |
| GPIO17 (XTAL32K) | | | | For AON I/O, the wake-up mode must be the same. | IE=0, PU=0, PD=0 |
| GPIO18 | | | | For AON I/O, the wake-up mode must be the same. | IE=0, PU=0, PD=0 |
| GPIO19 (ACOMP/ADC1) | | | | For AON I/O, the wake-up mode must be the same. | IE=0, PU=0, PD=0 |
| GPIO20 (ACOMP/ADC0) | | | | For PDS I/O, the wake-up mode must be the same. | IE=0, PU=0, PD=0 |
| GPIO21 | | | | For PDS I/O, the wake-up mode must be the same. | IE=0, PU=0, PD=0 |
| GPIO22 | | | | For PDS I/O, the wake-up mode must be the same. | IE=0, PU=0, PD=0 |
| GPIO23 | | | | For PDS I/O, the wake-up mode must be the same. | IE=0, PU=0, PD=0 |
| GPIO24 | | | | For PDS I/O, the wake-up mode must be the same. | IE=0, PU=0, PD=0 |
| GPIO25 | | | | For PDS I/O, the wake-up mode must be the same. | IE=0, PU=0, PD=0 |
| GPIO26 | | | | For PDS I/O, the wake-up mode must be the same. | IE=0, PU=0, PD=0 |
| GPIO27 (ADC10) | | | | For PDS I/O, the wake-up mode must be the same. | IE=0, PU=0, PD=0 |
| GPIO28 | | | | For PDS I/O, the wake-up mode must be the same | IE=0, PU=0, PD=0 |
| GPIO29 | | | | For PDS I/O, the wake-up mode must be the same | IE=0, PU=0, PD=0 |
| GPIO30 | | | | For PDS I/O, the wake-up mode must be the same | IE=0, PU=0, PD=0 |
| GPIO31 | | | | For PDS I/O, the wake-up mode must be the same | IE=0, PU=0, PD=0 |
| GPIO32 | | | | For PDS I/O, the wake-up mode must be the same | IE=0, PU=0, PD=0 |
| GPIO33 | | | | For PDS I/O, the wake-up mode must be the same | IE=0, PU=0, PD=0 |
| GPIO34 | | | | For PDS I/O, the wake-up mode must be the same | IE=0, PU=0, PD=0 |
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For PDS I/O, if rising edge wake-up is selected, it is necessary to ensure that the I/O is in
a low-level state before entering sleep. If the I/O is in a high-level state during sleep, it
will immediately trigger a wake-up.
Audio input or output can be connected to a 100K pull-up resistor. The AC coupling capacitors
in the subsequent stages filter out the DC component. Audio input only affects the bias
voltage.
The solution to the GPIO leakage issue of ADC measurement applications in PDS mode is shown
below. The following diagram shows the ADC measuring the voltage divider formed by R88 and R87
on the VCC battery through GPIO20. It uses an MOSFET controlled by a GPIO (for example, GPIO2)
to control the resistor voltage divider. In sleep mode, the MOSFET is turned off, and the
voltage of GPIO20 pull down to zero by R87, which ensures no leakage current at GPIO20.
| GPIO | Chip external PU/PD | Function | Wake-up method | Note | IE/PU/PD settings during sleep |
| --- | --- | --- | --- | --- | --- |
| GPIO0
(ADC9) | | | | For PDS I/O, the wake-up mode must be the same. | IE=0, PU=0, PD=0 |
| GPIO1
(ADC8) | | | | For PDS I/O, the wake-up mode must be the same. | IE=0, PU=0, PD=0 |
| GPIO2
(ACOMP/ADC2/Boot) | | | | For PDS I/O, the wake-up mode must be the same. | IE=0, PU=0, PD=0 |
| GPIO3 (ACOMP/ADC3) | | | | For PDS I/O, the wake-up mode must be the same. | IE=0, PU=0, PD=0 |
| GPIO10 (ACOMP/ADC7) | | | | For PDS I/O, the wake-up mode must be the same. | IE=0, PU=0, PD=0 |
| GPIO11 | | | | For PDS I/O, the wake-up mode must be the same. | IE=0, PU=0, PD=0 |
| GPIO12 (ACOMP/ADC6) | | | | For PDS I/O, the wake-up mode must be the same. | IE=0, PU=0, PD=0 |
| GPIO13 (ACOMP/ADC5) | | | | For PDS I/O, the wake-up mode must be the same. | IE=0, PU=0, PD=0 |
| GPIO14 (ACOMP/ADC4) | | | | For PDS I/O, the wake-up mode must be the same. | IE=0, PU=0, PD=0 |
| GPIO15 | | | | For PDS I/O, the wake-up mode must be the same. | IE=0, PU=0, PD=0 |
| GPIO16 (XTAL32K) | | | | For AON I/O, the wake-up mode must be the same. | IE=0, PU=0, PD=0 |
| GPIO17 (XTAL32K) | | | | For AON I/O, the wake-up mode must be the same. | IE=0, PU=0, PD=0 |
| GPIO20 (ACOMP/ADC0) | | | | For PDS I/O, the wake-up mode must be the same. | IE=0, PU=0, PD=0 |
| GPIO21 | | | | For PDS I/O, the wake-up mode must be the same. | IE=0, PU=0, PD=0 |
| GPIO22 | | | | For PDS I/O, the wake-up mode must be the same. | IE=0, PU=0, PD=0 |
| GPIO27 (ADC10) | | | | For PDS I/O, the wake-up mode must be the same. | IE=0, PU=0, PD=0 |
| GPIO28 | | | | For PDS I/O, the wake-up mode must be the same. | IE=0, PU=0, PD=0 |
| GPIO29 | | | | For PDS I/O, the wake-up mode must be the same. | IE=0, PU=0, PD=0 |
| GPIO30 | | | | For PDS I/O, the wake-up mode must be the same. | IE=0, PU=0, PD=0 |
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For PDS I/O, if rising edge wake-up is selected, it is necessary to ensure that the I/O is in
a low-level state before entering sleep. If the I/O is in a high-level state during sleep, it
will immediately trigger a wake-up.
Audio input or output can be connected to a 100K pull-up resistor. The AC coupling capacitors
in the subsequent stages filter out the DC component. Audio input only affects the bias
voltage.
The solution for addressing the leakage issue in PDS mode when measuring VCC\_battery voltage
using ADC is the same as the QCC744/QCC748.
Last Published: Apr 08, 2025
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