# Power
domain
Source: [https://docs.qualcomm.com/doc/80-WL740-8/topic/power_domain.html](https://docs.qualcomm.com/doc/80-WL740-8/topic/power_domain.html)
The power domains of the QCC74x are divided into digital and analog
domains.
Digital power domains include VDDIO1, VDDIO2, DVDD11, and
VDD18\_FLASH.
Analog power domains include AVDD33\_AON, PVDD33\_DCDC,
AVDD33\_RF1, AVDD33\_RF2, AVDD15\_RF1, AVDD15\_RF2, AVDD18\_RF, and
AVDD33\_RF3.
## Power pin function
Source: [https://docs.qualcomm.com/doc/80-WL740-8/topic/power_domain.html](https://docs.qualcomm.com/doc/80-WL740-8/topic/power_domain.html)
The function description of each power pin of QCC74x and the reference
current (not actual current) of the corresponding power pin are as follows:
Table : QCC743 power pin description
| Pin number | Pin name | Typical value | Direction | Function description | Design reference current |
| --- | --- | --- | --- | --- | --- |
| 2 | AVDD33\_RF1 | 3.3 V | IN | Power amplifier | 500 mA |
| 3 | AVDD33\_RF2 | 3.3 V | IN | Tx RF mixer | 50 mA |
| 8 | VDDIO1 | 3.3 V or 1.8 V | IN | GPIO 0, 1, 2, 3, 10, 11, 12, 13, 14, 15 | 160 mA |
| 18 | AVDD33\_AON | 3.3 V | IN | GPIO 16, 17 | 82 mA |
| 19 | VDD18\_FLASH | 1.8 V | — | Power pin; generated from internal LDO (3.3 V IN); need decoup cap; for
internal Flash | — |
| 20 | PVDD33\_DCDC | 3.3 V | IN | DCDC input power | 236 mA |
| 21 | SW\_DCDC | | — | Switch DCDC; connect 2.2 μH | — |
| 22 | DCDC\_OUT | 1.8 V | OUT | DCDC\_OUT, typical=1.8 V | 200 mA |
| 23 | DVDD11 | 1.1 V | — | Power pin; need decoup cap; generated from internal LDO (DCDC\_OUT=1.8 V
IN) | — |
| 24 | VDDIO\_IO | 3.3 V | IN | Input pin | 50 mA |
| 30 | VDDIO2 | 3.3 V or 1.8 V | IN | GPIO 20, 21, 22, 27, 28, 29, 30 | 250 mA |
| 37 | AVDD33\_RF3 | 3.3 V | IN | Input pin; for analog xtal | 50 mA |
| 38 | AVDD18\_RF | 1.8 V | IN | Input pin; from DCDC\_OUT=1.8 V; for CLKPLL | 50 mA |
| 39 | AVDD15\_RF2 | 1.5 V | — | Power pin; generated from internal LDO (DCDC\_OUT=1.8 V IN); need decoup cap
for analog RBB, LO | — |
| 40 | AVDD15\_RF1 | 1.5 V | — | Power pin; generated from internal LDO (DCDC\_OUT=1.8 V IN); need decoup cap
for analog LNA | — |
Table : QCC744 power pin description
| Pin number | Pin name | Typical value | Direction | Function description | Design reference current |
| --- | --- | --- | --- | --- | --- |
| 2 | AVDD33\_RF1 | 3.3 V | IN | Power amplifier | 500 mA |
| 3 | AVDD33\_RF2 | 3.3 V | IN | Tx RF mixer | 50 mA |
| 13 | VDDIO1 | 3.3 V or 1.8 V | IN | GPIO 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 | 256 mA |
| 26 | AVDD33\_AON | 3.3 V | IN | AON power, GPIO 16, 17, 18, 19 | 114 mA |
| 27 | VDD18\_FLASH | 1.8 V | — | Power pin; generated from internal LDO (3.3 V IN); need decoup cap; for
internal PSRAM | — |
| 28 | PVDD33\_DCDC | 3.3 V | IN | DCDC input power | 236 mA |
| 29 | SW\_DCDC | | — | Switch DCDC; connect 2.2 μH | — |
| 30 | DCDC\_OUT | 1.8 V | OUT | DCDC\_OUT; typical=1.8 V | 200 mA |
| 31 | DVDD11 | 1.1 V | — | Power pin; need decoup cap; generated from internal LDO (DCDC\_OUT=1.8 V IN);
for SoC | — |
| 32 | VDDIO\_IO | 3.3 V | IN | Input pin | |
| 42 | VDDIO2 | 3.3 V or 1.8 V | IN | GPIO 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,
34 | 240 mA |
| 53 | AVDD33\_RF3 | 3.3 V | IN | Input pin; for analog xtal | 50 mA |
| 54 | AVDD18\_RF | 1.8 V | IN | Input pin; from DCDC\_OUT=1.8 V; for CLKPLL | 50 mA |
| 55 | AVDD15\_RF2 | 1.5 V | — | Power pin; generated from internal LDO (DCDC\_OUT=1.8 V IN); need decoup cap
for analog RBB, LO | — |
| 56 | AVDD15\_RF1 | 1.5 V | — | Power pin; generated from internal LDO (DCDC\_OUT=1.8 V IN); need decoup cap
for analog LNA | — |
Table : QCC748 power pin description
| Pin number | Pin name | Typical value | Direction | Function description | Design reference current |
| --- | --- | --- | --- | --- | --- |
| 2 | AVDD33\_RF1 | 3.3 V | IN | Power amplifier | 500 mA |
| 3 | AVDD33\_RF2 | 3.3 V | IN | Tx RF mixer | 50 mA |
| 13 | VDDIO1 | 3.3 V or 1.8 V | IN | GPIO 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 | 256 mA |
| 26 | AVDD33\_AON | 3.3 V | IN | AON power, GPIO 16, 17, 18, 19 | 114 mA |
| 27 | VDD18\_FLASH | 1.8 V | — | Power pin; generated from internal LDO (3.3 V IN); need decoup cap; for internal
PSRAM | — |
| 28 | PVDD33\_DCDC | 3.3 V | IN | DCDC input power | 236 mA |
| 29 | SW\_DCDC | | — | Switch DCDC; connect 2.2 μH | — |
| 30 | DCDC\_OUT | 1.8 V | OUT | DCDC\_OUT; typical=1.8 V | 200 mA |
| 31 | DVDD11 | 1.1 V | — | Power pin; need decoup cap; generated from internal LDO (DCDC\_OUT=1.8 V IN); for
SoC | — |
| 32 | VDDIO\_USB | 3.3 V | IN | Input pin; for USB power | — |
| 42 | VDDIO2 | 3.3 V or 1.8 V | IN | GPIO 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34 | 240 mA |
| 53 | AVDD33\_RF3 | 3.3 V | IN | Input pin; for analog xtal | 50 mA |
| 54 | AVDD18\_RF | 1.8 V | IN | Input pin; from DCDC\_OUT=1.8 V; for CLKPLL | 50 mA |
| 55 | AVDD15\_RF2 | 1.5 V | — | Power pin; generated from internal LDO (DCDC\_OUT=1.8 V IN); need decoup cap for
analog RBB, LO | — |
| 56 | AVDD15\_RF1 | 1.5 V | — | Power pin; generated from internal LDO (DCDC\_OUT=1.8 V IN); need decoup cap for
analog LNA | — |
## AVDD33\_RF
Source: [https://docs.qualcomm.com/doc/80-WL740-8/topic/power_domain.html](https://docs.qualcomm.com/doc/80-WL740-8/topic/power_domain.html)
AVDD33\_RF1 and AVDD33\_RF2 provide power to the internal PA and TMX, respectively.
AVDD33\_RF1 requires a larger current when QCC74x is transmitting data
packets. To prevent a significant voltage drop due to insufficient current supply during
packet transmission, a 10 µF capacitor rated at twice 3.3 V (suggested rating above 10.0 V) is
recommended. In addition, the power supply circuit of this power pin operates at a frequency
of 2.4 GHz. To prevent the 2.4 GHz frequency component on the power supply from affecting the
performance of the internal circuit, recommend placing a capacitor with a self-resonant
frequency of 2.4 GHz at this pin, forming a low resistance to the “ground” to filter out
2.4 GHz frequency interference signals on the power supply.
Table : Schematic for the AVDD33_RF1 power pin
| QCC743 |  |
| --- | --- |
| QCC744/QCC748 |  |
AVDD33\_RF2 provides power to the TMX. A 100 nF capacitor with a voltage rating of 6.3 V
should be connected in parallel at this location to filter out high-frequency harmonics.
| QCC743 |  |
| --- | --- |
| QCC744/QCC748 |  |
| | |
AVDD33\_RF3 power pin powers the crystal circuit. A 100 nF capacitor with a voltage rating
of 6.3 V should be connected in parallel at this location to filter out high-frequency
harmonics.
Table : Schematic for the AVDD33_RF3 power pin
| QCC743 |  |
| --- | --- |
| QCC744/QCC748 |  |
## DCDC
Source: [https://docs.qualcomm.com/doc/80-WL740-8/topic/power_domain.html](https://docs.qualcomm.com/doc/80-WL740-8/topic/power_domain.html)
The PVDD33\_DCDC power pin supplies the internal DCDC circuitry. To meet the transient
current demands of various circuit modules under this power supply, a 4.7 µF capacitor with a
voltage rating above 6.3 V is recommended.
Table : Schematic for the PVDD33_DCDC power pin
| QCC743 |  |
| --- | --- |
| QCC744/QCC748 |  |
When QCC74x is operating in DCDC mode, a 2.2 µH inductor should be
connected between SW\_DCDC and DCDC\_OUT pins. The maximum rated current of the inductor should
be more than 200 mA and the DC resistance should be less than 0.15 Ω. The part number of the
recommended component is DFE201612E-2R2M. Furthermore, to ensure a cleaner DCDC\_OUT output
with less ripple, recommend placing a 4.7 µF capacitor near the DCDC\_OUT pin, with a voltage
rating of 6.3 V.
When QCC74x is operating in LDO mode, the inductor between SW\_DCDC and
DCDC\_OUT can be omitted, and the DCDC\_OUT pin can be connected to the 3.3 V power supply. The
previously connected 4.7 µF capacitor should still be retained.
For compatibility with both DCDC and LDO modes, suggest reserving a 0 R resistor at the
DCDC\_OUT pin for connection to the 3.3 V power supply during the early stages of schematic
design.
Additionally, the AVDD18\_RF pin (can input 3.3 V voltage) powers the CLKPLL circuit
section and also supplies the internal LDO\_1V5 and LDO\_1V1. A 100 nF capacitor with a voltage
rating of 6.3 V should be connected in parallel at this location to filter out high-frequency
harmonics.
Table : Schematic for the SW_DCDC and DCDC_OUT power pins
| QCC743 |  |
| --- | --- |
| QCC744/QCC748 |  |
## AVDD15\_RF
Source: [https://docs.qualcomm.com/doc/80-WL740-8/topic/power_domain.html](https://docs.qualcomm.com/doc/80-WL740-8/topic/power_domain.html)
The AVDD15\_RF1 and AVDD15\_RF2 power pins provide power to various submodules in the RF
transmit and receive chains. These pins are generated by the internal LDO of QCC74x. These two power pins should externally share a 2.2 µF capacitor with a
voltage tolerance of 6.3 V, and a 10 pF capacitor. The purpose of the 2.2 µF capacitor is to
filter out ripples in the power supply and provide stable current to each subcircuit in the RF
chain, as well as to increase the stability of the internal LDO circuit. The 10 pF capacitor
serves as a low impedance to the ground, filtering out 2.4 GHz frequency interference on the
power supply.
Table : Schematic for the AVDD15 power pin
| QCC743 |  |
| --- | --- |
| QCC744/QCC748 |  |
## AVDD33\_AON
Source: [https://docs.qualcomm.com/doc/80-WL740-8/topic/power_domain.html](https://docs.qualcomm.com/doc/80-WL740-8/topic/power_domain.html)
The AVDD33\_AON pin must be powered on continuously, even when QCC74x is
in sleep mode. Some circuits under this power domain will still operate. A 100 nF capacitor
with a voltage rating of 6.3 V is recommended to be placed in parallel at this power pin, used
for filtering high-frequency harmonics.
Table : Schematic for the AVDD33_AON power pin
| QCC743 |  |
| --- | --- |
| QCC744/QCC748 |  |
## DVDD11
Source: [https://docs.qualcomm.com/doc/80-WL740-8/topic/power_domain.html](https://docs.qualcomm.com/doc/80-WL740-8/topic/power_domain.html)
The recommended schematic designs for each digital power domain of QCC74x
are as follows:
VDDIO1 and VDDIO2 are two power pins that provide power to different digital I/O. Both
3.3 V and 1.8 V input supplies are supported. Recommend to add an extra 100 nF capacitor with
a voltage rating of 6.3 V close to each digital power supply pin, used for filtering
high-frequency harmonics.
Table : Schematic for the VDDIO power pin
| QCC743 |  |
| --- | --- |
| QCC744/QCC748 |  |
The DVDD11 power pin is used to power the internal core (CPU) of the QCC74x. This power supply is generated by the internal LDO\_1V1 of QCC74x. To
increase the stability of this LDO, recommend connecting a 4.7 µF (for QCC743)/ 2.2 µF (for
QCC744/QCC748) capacitor in parallel at this power pin, with a voltage rating of
6.3 V.
Table : Schematic for the DVDD11 power pin
| QCC743 |  |
| --- | --- |
| QCC744/QCC748 |  |
The VDD18\_FLASH power pin is used to power the embedded Flash. This power supply is
generated by the internal LDO\_1V8 of QCC74x. To increase the stability of this
LDO, recommend connecting a 4.7 µF capacitor in parallel at this power pin, with a voltage
rating of 6.3 V.
Table : Schematic for the VDD18_FLASH power pin
| QCC743 |  |
| --- | --- |
| QCC744/QCC748 |  |
Recommended connecting a 10 nF capacitor in parallel at the VDD33 power pin, with a
voltage rating of 6.3 V.
Table : Schematic for the VDD33 power pin
| QCC743 |  |
| --- | --- |
| QCC744/QCC748 |  |
Last Published: Apr 08, 2025
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