# Pin definitions Source: [https://docs.qualcomm.com/doc/80-WL743-1/topic/pin-definitions.html](https://docs.qualcomm.com/doc/80-WL743-1/topic/pin-definitions.html) ## I/O parameter definitions Source: [https://docs.qualcomm.com/doc/80-WL743-1/topic/pin-definitions.html](https://docs.qualcomm.com/doc/80-WL743-1/topic/pin-definitions.html) | **Symbol** | **Description** | | --- | --- | | ***Pin attribute*** | ***Pin attribute*** | | AI | Analog input (does not include pin circuitry) | | AO | Analog output (does not include pin circuitry) | | B | Bidirectional digital with CMOS input | | DI | Digital input (CMOS) | | DO | Digital output (CMOS) | | H | High-voltage tolerant | | S | Schmitt trigger input | | Z | High-impedance (Hi-Z) output | | ***Pin pull details for digital I/Os*** | ***Pin pull details for digital I/Os*** | | nppdpukp | Programmable pull resistor. The default pull direction is indicated
using capital letters, and is a prefix to other programmable options:

NP: pdpukp = default no-pull, with programmable options following
the colon (:)


PD: nppukp = default pull-down, with
programmable options following the colon (:)


PU: nppdkp =
default pull-up, with programmable options following the colon
(:)


KP: nppdpu = default keeper, with programmable options
following the colon (:) | | KP | Contains an internal weak keeper device (keepers cannot drive
external buses) | | NP | Contains no internal pull | | PU | Contains an internal pull-up device | | PD | Contains an internal pull-down device | ## Pin assignments Source: [https://docs.qualcomm.com/doc/80-WL743-1/topic/pin-definitions.html](https://docs.qualcomm.com/doc/80-WL743-1/topic/pin-definitions.html) ### Pin map Source: [https://docs.qualcomm.com/doc/80-WL743-1/topic/pin-definitions.html](https://docs.qualcomm.com/doc/80-WL743-1/topic/pin-definitions.html) QCC743 40-pin package includes 15 fixed power ports, 4 fixed analog ports, and up to 19 configurable GPIO ports. Figure : QCC743 pin assignments Page-1 Sheet.1 11 11 Sheet.2 12 12 Sheet.3 13 13 Sheet.4 14 14 Sheet.5 15 15 Sheet.6 16 16 Sheet.7 17 17 Sheet.8 18 18 Sheet.9 19 19 Sheet.10 20 20 Sheet.11 Sheet.12 Sheet.13 Sheet.14 Sheet.15 Sheet.16 Sheet.17 Sheet.18 Sheet.19 Sheet.20 Sheet.21 Sheet.22 Sheet.23 Sheet.24 Sheet.25 Sheet.26 Sheet.27 Sheet.28 Sheet.29 QCC743 5.0 x 5.0 mm 40-pin QFN QCC7435.0 x 5.0 mm40-pin QFN Sheet.30 PAD_GPIO_21 GPIO_21 Sheet.31 PAD_GPIO_20 GPIO_20 Sheet.32 USB_DM NC Sheet.33 USB_DP NC Sheet.34 VDDIO_USB VDD33 Sheet.35 DVDD11 DVDD11 Sheet.36 DCDC_OUT DCDC_OUT Sheet.37 SW_DCDC SW_DCDC Sheet.38 21 21 Sheet.39 22 22 Sheet.40 23 23 Sheet.41 24 24 Sheet.42 25 25 Sheet.43 26 26 Sheet.44 27 27 Sheet.45 28 28 Sheet.46 29 29 Sheet.47 30 30 Sheet.48 31 31 Sheet.49 32 32 Sheet.50 33 33 Sheet.51 34 34 Sheet.52 35 35 Sheet.53 36 36 Sheet.54 37 37 Sheet.55 38 38 Sheet.56 39 39 Sheet.57 40 40 Sheet.58 VDD18_FLASH VDD18_FLASH Sheet.59 PVDD33_DCDC PVDD33_DCDC Sheet.60 PAD_GPIO_15 GPIO_15 Sheet.61 PAD_GPIO_16 GPIO_16 Sheet.62 PAD_GPIO_17 GPIO_17 Sheet.63 CHIP_EN CHIP_EN Sheet.64 AVDD33_AON AVDD33_AON Sheet.65 AVDD15_RF2 AVDD15_RF2 Sheet.66 AVDD18_RF AVDD18_RF Sheet.67 AVDD33_RF3 AVDD33_RF3 Sheet.68 XTAL_OUT XTAL_OUT Sheet.69 XTAL_IN XTAL_IN Sheet.70 PAD_GPIO_30 GPIO_30 Sheet.71 PAD_GPIO_12 GPIO_12 Sheet.72 PAD_GPIO_27 GPIO_27 Sheet.73 PAD_GPIO_13 GPIO_13 Sheet.74 PAD_GPIO_14 GPIO_14 Sheet.75 PAD_GPIO_22 GPIO_22 Sheet.76 VDDIO2 VDDIO2 Sheet.77 PAD_GPIO_28 GPIO_28 Sheet.78 PAD_GPIO_29 GPIO_29 Sheet.79 AVDD15_RF1 AVDD15_RF1 Sheet.80 Sheet.81 1 1 Sheet.82 2 2 Sheet.83 3 3 Sheet.84 4 4 Sheet.85 5 5 Sheet.86 6 6 Sheet.87 7 7 Sheet.88 8 8 Sheet.89 9 9 Sheet.90 10 10 Sheet.91 AVDD33_RF1 AVDD33_RF1 Sheet.92 AVDD33_RF2 AVDD33_RF2 Sheet.93 PAD_GPIO_0 GPIO_0 Sheet.94 PAD_GPIO_1 GPIO_1 Sheet.95 PAD_GPIO_2 GPIO_2 Sheet.96 PAD_GPIO_3 GPIO_3 Sheet.97 PAD_GPIO_10 GPIO_10 Sheet.98 PAD_GPIO_11 GPIO_11 Sheet.99 VDDIO1 VDDIO1 Sheet.100 ANT ANT QCC744 56-pin package includes 15 fixed power ports, 4 fixed analog ports, and up to 35 configurable GPIO ports. Figure : QCC744 pin assignments Page-1 Sheet.1 15 15 Sheet.2 16 16 Sheet.3 17 17 Sheet.4 18 18 Sheet.5 19 19 Sheet.6 20 20 Sheet.7 21 21 Sheet.8 22 22 Sheet.9 23 23 Sheet.10 24 24 Sheet.11 Sheet.12 Sheet.13 Sheet.14 Sheet.15 Sheet.16 Sheet.17 Sheet.18 Sheet.19 Sheet.20 Sheet.21 Sheet.22 Sheet.23 Sheet.24 Sheet.25 Sheet.26 Sheet.27 Sheet.28 Sheet.29 Sheet.30 Sheet.31 Sheet.32 Sheet.33 Sheet.34 Sheet.35 Sheet.36 Sheet.37 QCC744 7.0 x 7.0 mm 56-pin QFN QCC7447.0 x 7.0 mm56-pin QFN Sheet.38 PAD_GPIO_21 GPIO_21 Sheet.39 PAD_GPIO_20 GPIO_20 Sheet.40 USB_DM NC Sheet.41 USB_DP NC Sheet.42 VDDIO_USB VDD33 Sheet.43 DVDD11 DVDD11 Sheet.44 DCDC_OUT DCDC_OUT Sheet.45 SW_DCDC SW_DCDC Sheet.46 29 29 Sheet.47 30 30 Sheet.48 31 31 Sheet.49 32 32 Sheet.50 33 33 Sheet.51 34 34 Sheet.52 35 35 Sheet.53 36 36 Sheet.54 37 37 Sheet.55 38 38 Sheet.56 47 47 Sheet.57 48 48 Sheet.58 49 49 Sheet.59 50 50 Sheet.60 51 51 Sheet.61 52 52 Sheet.62 53 53 Sheet.63 54 54 Sheet.64 55 55 Sheet.65 56 56 Sheet.66 PAD_GPIO_18 GPIO_18 Sheet.67 PAD_GPIO_19 GPIO_19 Sheet.68 PAD_GPIO_13 GPIO_13 Sheet.69 PAD_GPIO_14 GPIO_14 Sheet.70 PAD_GPIO_15 GPIO_15 Sheet.71 PAD_GPIO_16 GPIO_16 Sheet.72 PAD_GPIO_17 GPIO_17 Sheet.73 AVDD15_RF2 AVDD15_RF2 Sheet.74 AVDD18_RF AVDD18_RF Sheet.75 AVDD33_RF3 AVDD33_RF3 Sheet.76 XTANL_OUT XTAL_OUT Sheet.77 XTAL_IN XTAL_IN Sheet.78 PAD_GPIO_34 GPIO_34 Sheet.79 PAD_GPIO_10 GPIO_10 Sheet.80 PAD_GPIO_31 GPIO_31 Sheet.81 PAD_GPIO_11 GPIO_11 Sheet.82 PAD_GPIO_12 GPIO_12 Sheet.83 PAD_GPIO_22 GPIO_22 Sheet.84 PAD_GPIO_23 GPIO_23 Sheet.85 PAD_GPIO_32 GPIO_32 Sheet.86 PAD_GPIO_33 GPIO_33 Sheet.87 AVDD15_RF1 AVDD15_RF1 Sheet.88 Sheet.89 1 1 Sheet.90 2 2 Sheet.91 3 3 Sheet.92 4 4 Sheet.93 5 5 Sheet.94 6 6 Sheet.95 7 7 Sheet.96 8 8 Sheet.97 9 9 Sheet.98 10 10 Sheet.99 AVDD33_RF1 AVDD33_RF1 Sheet.100 AVDD33_RF2 AVDD33_RF2 Sheet.101 PAD_GPIO_0 GPIO_0 Sheet.102 PAD_GPIO_1 GPIO_1 Sheet.103 PAD_GPIO_2 GPIO_2 Sheet.104 PAD_GPIO_3 GPIO_3 Sheet.105 PAD_GPIO_5 GPIO_5 Sheet.106 PAD_GPIO_6 GPIO_6 Sheet.107 PAD_GPIO_4 GPIO_4 Sheet.108 ANT ANT Sheet.109 11 11 Sheet.110 12 12 Sheet.111 13 13 Sheet.112 14 14 Sheet.113 PAD_GPIO_7 GPIO_7 Sheet.114 VDDIO1 VDDIO1 Sheet.115 PAD_GPIO_9 GPIO_9 Sheet.116 PAD_GPIO_8 GPIO_8 Sheet.117 PAD_GPIO_25 GPIO_25 Sheet.118 PAD_GPIO_24 GPIO_24 Sheet.119 39 39 Sheet.120 40 40 Sheet.121 41 41 Sheet.122 42 42 Sheet.123 PAD_GPIO_26 GPIO_26 Sheet.124 VDDIO2 VDDIO2 Sheet.125 43 43 Sheet.126 44 44 Sheet.127 45 45 Sheet.128 46 46 Sheet.129 PAD_GPIO_30 GPIO_30 Sheet.130 PAD_GPIO_27 GPIO_27 Sheet.131 PAD_GPIO_28 GPIO_28 Sheet.132 PAD_GPIO_29 GPIO_29 Sheet.133 25 25 Sheet.134 26 26 Sheet.135 27 27 Sheet.136 28 28 Sheet.137 VDD18_FLASH VDD18_FLASH Sheet.138 PVDD33_DCDC PVDD33_DCDC Sheet.139 CHIP_EN CHIP_EN Sheet.140 AVDD33_AON AVDD33_AON ### Pin descriptions Source: [https://docs.qualcomm.com/doc/80-WL743-1/topic/pin-definitions.html](https://docs.qualcomm.com/doc/80-WL743-1/topic/pin-definitions.html) | QCC743 | QCC744 | Voltage domain | Type | Pin name | GPIO function select number | Peripheral internal function select | PAD main function | Description | | --- | --- | --- | --- | --- | --- | --- | --- | --- | | 1 | 1 | AVDD15\_RF1 | Analog | ANT | - | - | ANT | RF signal pin | | 2 | 2 | - | Power, Input | AVDD33\_RF1 | - | - | AVDD33\_RF1 | RF transmitter power supply, 3.3 V | | 3 | 3 | - | Power, Input | AVDD33\_RF2 | - | - | AVDD33\_RF2 | RF transmitter power supply, 3.3 V | | 4 | 4 | VDDIO\_1 | DI/DO | GPIO\_0 | 0 | - | - | - | | 4 | 4 | VDDIO\_1 | DI/DO | GPIO\_0 | 1 | - | SPI\_SS | SPI Slave Select | | 4 | 4 | VDDIO\_1 | DI/DO | GPIO\_0 | 2 | - | - | - | | 4 | 4 | VDDIO\_1 | DI/DO | GPIO\_0 | 3 | - | I2S\_BCLK | I^2^S Bit Clock | | 4 | 4 | VDDIO\_1 | DI/DO | GPIO\_0 | 4 | - | - | - | | 4 | 4 | VDDIO\_1 | DI/DO | GPIO\_0 | 5 | - | I2C0\_SCL | I^2^C 0 Serial Clock | | 4 | 4 | VDDIO\_1 | DI/DO | GPIO\_0 | 6 | - | I2C1\_SCL | I^2^C 1 Serial Clock | | 4 | 4 | VDDIO\_1 | DI/DO | GPIO\_0 | 7 | uart\_sig\_0\_sel=0 | UART0\_RTS | UART 0 Request To Send | | 4 | 4 | VDDIO\_1 | DI/DO | GPIO\_0 | 7 | uart\_sig\_0\_sel=1 | UART0\_CTS | UART 0 Clear To Send | | 4 | 4 | VDDIO\_1 | DI/DO | GPIO\_0 | 7 | uart\_sig\_0\_sel=2 | UART0\_TXD | UART 0 Transmit Data | | 4 | 4 | VDDIO\_1 | DI/DO | GPIO\_0 | 7 | uart\_sig\_0\_sel=3 | UART0\_RXD | UART 0 Receive Data | | 4 | 4 | VDDIO\_1 | DI/DO | GPIO\_0 | 7 | uart\_sig\_0\_sel=4 | UART1\_RTS | UART 1 Request To Send | | 4 | 4 | VDDIO\_1 | DI/DO | GPIO\_0 | 7 | uart\_sig\_0\_sel=5 | UART1\_CTS | UART 1 Clear To Send | | 4 | 4 | VDDIO\_1 | DI/DO | GPIO\_0 | 7 | uart\_sig\_0\_sel=6 | UART1\_TXD | UART 1 Transmit Data | | 4 | 4 | VDDIO\_1 | DI/DO | GPIO\_0 | 7 | uart\_sig\_0\_sel=7 | UART1\_RXD | UART 1 Receive Data | | 4 | 4 | VDDIO\_1 | DI/DO | GPIO\_0 | 7 | uart\_sig\_0\_sel=8 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 4 | 4 | VDDIO\_1 | DI/DO | GPIO\_0 | 7 | uart\_sig\_0\_sel=9 | - | - | | 4 | 4 | VDDIO\_1 | DI/DO | GPIO\_0 | 7 | uart\_sig\_0\_sel=10 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 4 | 4 | VDDIO\_1 | DI/DO | GPIO\_0 | 7 | uart\_sig\_0\_sel=11 | ISO11898\_RXD | CAN (ISO11898) Receive Data | | 4 | 4 | VDDIO\_1 | DI/DO | GPIO\_0 | 8 | - | - | - | | 4 | 4 | VDDIO\_1 | DI/DO | GPIO\_0 | 9 | - | CAM1\_VSYNC | Camera 1 Vertical Sync (QCC744) | | 4 | 4 | VDDIO\_1 | DI/DO | GPIO\_0 | 10 | - | ADC\_CH9 | ADC Channel 9 | | 4 | 4 | VDDIO\_1 | DI/DO | GPIO\_0 | 11 | - | SWGPIO0 | Software GPIO 0 | | 4 | 4 | VDDIO\_1 | DI/DO | GPIO\_0 | 12 | - | - | - | | 4 | 4 | VDDIO\_1 | DI/DO | GPIO\_0 | 16 | reg\_pwm1\_io\_sel=0 | PWM0\_CH0P | PWM 0 Channel 0 Positive | | 4 | 4 | VDDIO\_1 | DI/DO | GPIO\_0 | 16 | reg\_pwm1\_io\_sel=1 | PWM0\_CH0P | PWM 0 Channel 0 Positive | | 4 | 4 | VDDIO\_1 | DI/DO | GPIO\_0 | 22 | - | - | - | | 4 | 4 | VDDIO\_1 | DI/DO | GPIO\_0 | 23 | - | - | - | | 4 | 4 | VDDIO\_1 | DI/DO | GPIO\_0 | 24 | - | - | - | | 4 | 4 | VDDIO\_1 | DI/DO | GPIO\_0 | 25 | - | - | - | | 4 | 4 | VDDIO\_1 | DI/DO | GPIO\_0 | 26 | - | M0\_JTAG\_TMS | M0 JTAG Test Mode Select | | 5 | 5 | VDDIO\_1 | DI/DO | GPIO\_1 | 0 | - | - | - | | 5 | 5 | VDDIO\_1 | DI/DO | GPIO\_1 | 1 | - | SPI\_SCLK | SPI Serial Clock | | 5 | 5 | VDDIO\_1 | DI/DO | GPIO\_1 | 2 | - | - | - | | 5 | 5 | VDDIO\_1 | DI/DO | GPIO\_1 | 3 | - | I2S\_FS | I^2^S Frame Sync | | 5 | 5 | VDDIO\_1 | DI/DO | GPIO\_1 | 4 | - | - | - | | 5 | 5 | VDDIO\_1 | DI/DO | GPIO\_1 | 5 | - | I2C0\_SDA | I^2^C 0 Serial Data | | 5 | 5 | VDDIO\_1 | DI/DO | GPIO\_1 | 6 | - | I2C1\_SDA | I^2^C 1 Serial Data | | 5 | 5 | VDDIO\_1 | DI/DO | GPIO\_1 | 7 | uart\_sig\_1\_sel=0 | UART0\_RTS | UART 0 Request To Send | | 5 | 5 | VDDIO\_1 | DI/DO | GPIO\_1 | 7 | uart\_sig\_1\_sel=1 | UART0\_CTS | UART 0 Clear To Send | | 5 | 5 | VDDIO\_1 | DI/DO | GPIO\_1 | 7 | uart\_sig\_1\_sel=2 | UART0\_TXD | UART 0 Transmit Data | | 5 | 5 | VDDIO\_1 | DI/DO | GPIO\_1 | 7 | uart\_sig\_1\_sel=3 | UART0\_RXD | UART 0 Receive Data | | 5 | 5 | VDDIO\_1 | DI/DO | GPIO\_1 | 7 | uart\_sig\_1\_sel=4 | UART1\_RTS | UART 1 Request To Send | | 5 | 5 | VDDIO\_1 | DI/DO | GPIO\_1 | 7 | uart\_sig\_1\_sel=5 | UART1\_CTS | UART 1 Clear To Send | | 5 | 5 | VDDIO\_1 | DI/DO | GPIO\_1 | 7 | uart\_sig\_1\_sel=6 | UART1\_TXD | UART 1 Transmit Data | | 5 | 5 | VDDIO\_1 | DI/DO | GPIO\_1 | 7 | uart\_sig\_1\_sel=7 | UART1\_RXD | UART 1 Receive Data | | 5 | 5 | VDDIO\_1 | DI/DO | GPIO\_1 | 7 | uart\_sig\_1\_sel=8 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 5 | 5 | VDDIO\_1 | DI/DO | GPIO\_1 | 7 | uart\_sig\_1\_sel=9 | - | - | | 5 | 5 | VDDIO\_1 | DI/DO | GPIO\_1 | 7 | uart\_sig\_1\_sel=10 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 5 | 5 | VDDIO\_1 | DI/DO | GPIO\_1 | 7 | uart\_sig\_1\_sel=11 | ISO11898\_RXD | CAN (ISO 11898) Receive Data | | 5 | 5 | VDDIO\_1 | DI/DO | GPIO\_1 | 8 | - | - | - | | 5 | 5 | VDDIO\_1 | DI/DO | GPIO\_1 | 9 | - | CAM1\_HSYNC | Camera 1 Horizontal Sync (QCC744) | | 5 | 5 | VDDIO\_1 | DI/DO | GPIO\_1 | 10 | - | ADC\_CH8 | ADC Channel 8 | | 5 | 5 | VDDIO\_1 | DI/DO | GPIO\_1 | 11 | - | SWGPIO1 | Software GPIO1 | | 5 | 5 | VDDIO\_1 | DI/DO | GPIO\_1 | 12 | - | - | - | | 5 | 5 | VDDIO\_1 | DI/DO | GPIO\_1 | 16 | reg\_pwm1\_io\_sel=0 | PWM0\_CH1P | PWM 0 Channel 1 Positive | | 5 | 5 | VDDIO\_1 | DI/DO | GPIO\_1 | 16 | reg\_pwm1\_io\_sel=1 | PWM0\_CH0N | PWM 0 Channel 0 Negative | | 5 | 5 | VDDIO\_1 | DI/DO | GPIO\_1 | 22 | - | - | - | | 5 | 5 | VDDIO\_1 | DI/DO | GPIO\_1 | 23 | - | - | - | | 5 | 5 | VDDIO\_1 | DI/DO | GPIO\_1 | 24 | - | - | - | | 5 | 5 | VDDIO\_1 | DI/DO | GPIO\_1 | 25 | - | - | - | | 5 | 5 | VDDIO\_1 | DI/DO | GPIO\_1 | 26 | - | M0\_JTAG\_TCK | M0 JTAG Test Clock | | 6 | 6 | VDDIO\_1 | DI/DO | GPIO\_2 | 0 | - | - | | | 6 | 6 | VDDIO\_1 | DI/DO | GPIO\_2 | 1 | - | SPI\_MISO | SPI Master Input, Slave Output | | 6 | 6 | VDDIO\_1 | DI/DO | GPIO\_2 | 2 | - | - | - | | 6 | 6 | VDDIO\_1 | DI/DO | GPIO\_2 | 3 | - | I2S\_DI/I2S\_RCLK\_O | I^2^S Data Input/I^2^S Receive Clock Output | | 6 | 6 | VDDIO\_1 | DI/DO | GPIO\_2 | 4 | - | - | - | | 6 | 6 | VDDIO\_1 | DI/DO | GPIO\_2 | 5 | - | I2C0\_SCL | I^2^C 0 Serial Clock | | 6 | 6 | VDDIO\_1 | DI/DO | GPIO\_2 | 6 | - | I2C1\_SCL | I^2^C 1 Serial Clock | | 6 | 6 | VDDIO\_1 | DI/DO | GPIO\_2 | 7 | uart\_sig\_2\_sel=0 | UART0\_RTS | UART 0 Request To Send | | 6 | 6 | VDDIO\_1 | DI/DO | GPIO\_2 | 7 | uart\_sig\_2\_sel=1 | UART0\_CTS | UART 0 Clear To Send | | 6 | 6 | VDDIO\_1 | DI/DO | GPIO\_2 | 7 | uart\_sig\_2\_sel=2 | UART0\_TXD | UART 0 Transmit Data | | 6 | 6 | VDDIO\_1 | DI/DO | GPIO\_2 | 7 | uart\_sig\_2\_sel=3 | UART0\_RXD | UART 0 Receive Data | | 6 | 6 | VDDIO\_1 | DI/DO | GPIO\_2 | 7 | uart\_sig\_2\_sel=4 | UART1\_RTS | UART 1 Request To Send | | 6 | 6 | VDDIO\_1 | DI/DO | GPIO\_2 | 7 | uart\_sig\_2\_sel=5 | UART1\_CTS | UART 1 Clear To Send | | 6 | 6 | VDDIO\_1 | DI/DO | GPIO\_2 | 7 | uart\_sig\_2\_sel=6 | UART1\_TXD | UART 1 Transmit Data | | 6 | 6 | VDDIO\_1 | DI/DO | GPIO\_2 | 7 | uart\_sig\_2\_sel=7 | UART1\_RXD | UART 1 Receive Data | | 6 | 6 | VDDIO\_1 | DI/DO | GPIO\_2 | 7 | uart\_sig\_2\_sel=8 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 6 | 6 | VDDIO\_1 | DI/DO | GPIO\_2 | 7 | uart\_sig\_2\_sel=9 | - | - | | 6 | 6 | VDDIO\_1 | DI/DO | GPIO\_2 | 7 | uart\_sig\_2\_sel=10 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 6 | 6 | VDDIO\_1 | DI/DO | GPIO\_2 | 7 | uart\_sig\_2\_sel=11 | ISO11898\_RXD | CAN (ISO 11898) Receive Data | | 6 | 6 | VDDIO\_1 | DI/DO | GPIO\_2 | 8 | - | - | - | | 6 | 6 | VDDIO\_1 | DI/DO | GPIO\_2 | 9 | - | - | - | | 6 | 6 | VDDIO\_1 | DI/DO | GPIO\_2 | 10 | - | ADC\_CH2 | ADC Channel 2 | | 6 | 6 | VDDIO\_1 | DI/DO | GPIO\_2 | 11 | - | SWGPIO2 | Software GPIO 2 | | 6 | 6 | VDDIO\_1 | DI/DO | GPIO\_2 | 12 | - | - | - | | 6 | 6 | VDDIO\_1 | DI/DO | GPIO\_2 | 16 | reg\_pwm1\_io\_sel=0 | PWM0\_CH2P | PWM 0 Channel 2 Positive | | 6 | 6 | VDDIO\_1 | DI/DO | GPIO\_2 | 16 | reg\_pwm1\_io\_sel=1 | PWM0\_CH1P | PWM 0 Channel 1 Positive | | 6 | 6 | VDDIO\_1 | DI/DO | GPIO\_2 | 22 | - | - | - | | 6 | 6 | VDDIO\_1 | DI/DO | GPIO\_2 | 23 | - | - | - | | 6 | 6 | VDDIO\_1 | DI/DO | GPIO\_2 | 24 | - | - | - | | 6 | 6 | VDDIO\_1 | DI/DO | GPIO\_2 | 25 | - | - | - | | 6 | 6 | VDDIO\_1 | DI/DO | GPIO\_2 | 26 | - | M0\_JTAG\_TDO | M0 JTAG Test Data Out | | 7 | 7 | VDDIO\_1 | DI/DO | GPIO\_3 | 0 | - | - | - | | 7 | 7 | VDDIO\_1 | DI/DO | GPIO\_3 | 1 | - | SPI\_MOSI | SPI Master Output, Slave Input | | 7 | 7 | VDDIO\_1 | DI/DO | GPIO\_3 | 2 | - | - | - | | 7 | 7 | VDDIO\_1 | DI/DO | GPIO\_3 | 3 | - | I2S\_DO/I2S\_RCLK\_O | I^2^S Data Output/I^2^S Receive Clock
Output | | 7 | 7 | VDDIO\_1 | DI/DO | GPIO\_3 | 4 | - | - | - | | 7 | 7 | VDDIO\_1 | DI/DO | GPIO\_3 | 5 | - | I2C0\_SDA | I^2^C 0 Serial Data | | 7 | 7 | VDDIO\_1 | DI/DO | GPIO\_3 | 6 | - | I2C1\_SDA | I^2^C 1 Serial Data | | 7 | 7 | VDDIO\_1 | DI/DO | GPIO\_3 | 7 | uart\_sig\_3\_sel=0 | UART0\_RTS | UART 0 Request To Send | | 7 | 7 | VDDIO\_1 | DI/DO | GPIO\_3 | 7 | uart\_sig\_3\_sel=1 | UART0\_CTS | UART 0 Clear To Send | | 7 | 7 | VDDIO\_1 | DI/DO | GPIO\_3 | 7 | uart\_sig\_3\_sel=2 | UART0\_TXD | UART 0 Transmit Data | | 7 | 7 | VDDIO\_1 | DI/DO | GPIO\_3 | 7 | uart\_sig\_3\_sel=3 | UART0\_RXD | UART 0 Receive Data | | 7 | 7 | VDDIO\_1 | DI/DO | GPIO\_3 | 7 | uart\_sig\_3\_sel=4 | UART1\_RTS | UART 1 Request To Send | | 7 | 7 | VDDIO\_1 | DI/DO | GPIO\_3 | 7 | uart\_sig\_3\_sel=5 | UART1\_CTS | UART 1 Clear To Send | | 7 | 7 | VDDIO\_1 | DI/DO | GPIO\_3 | 7 | uart\_sig\_3\_sel=6 | UART1\_TXD | UART 1 Transmit Data | | 7 | 7 | VDDIO\_1 | DI/DO | GPIO\_3 | 7 | uart\_sig\_3\_sel=7 | UART1\_RXD | UART 1 Receive Data | | 7 | 7 | VDDIO\_1 | DI/DO | GPIO\_3 | 7 | uart\_sig\_3\_sel=8 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 7 | 7 | VDDIO\_1 | DI/DO | GPIO\_3 | 7 | uart\_sig\_3\_sel=9 | - | - | | 7 | 7 | VDDIO\_1 | DI/DO | GPIO\_3 | 7 | uart\_sig\_3\_sel=10 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 7 | 7 | VDDIO\_1 | DI/DO | GPIO\_3 | 7 | uart\_sig\_3\_sel=11 | ISO11898\_RXD | CAN (ISO 11898) Receive Data | | 7 | 7 | VDDIO\_1 | DI/DO | GPIO\_3 | 8 | - | - | - | | 7 | 7 | VDDIO\_1 | DI/DO | GPIO\_3 | 9 | - | CAM1\_DAT0 | Camera 1 Data 0 (QCC744) | | 7 | 7 | VDDIO\_1 | DI/DO | GPIO\_3 | 10 | - | ADC\_CH3 | ADC Channel 3 | | 7 | 7 | VDDIO\_1 | DI/DO | GPIO\_3 | 11 | - | SWGPIO3 | Software GPIO 3 | | 7 | 7 | VDDIO\_1 | DI/DO | GPIO\_3 | 12 | - | - | - | | 7 | 7 | VDDIO\_1 | DI/DO | GPIO\_3 | 16 | reg\_pwm1\_io\_sel=0 | PWM0\_CH3P | PWM 0 Channel 3 Positive | | 7 | 7 | VDDIO\_1 | DI/DO | GPIO\_3 | 16 | reg\_pwm1\_io\_sel=1 | PWM0\_CH1N | PWM 0 Channel 1 Negative | | 7 | 7 | VDDIO\_1 | DI/DO | GPIO\_3 | 22 | - | - | - | | 7 | 7 | VDDIO\_1 | DI/DO | GPIO\_3 | 23 | - | - | - | | 7 | 7 | VDDIO\_1 | DI/DO | GPIO\_3 | 24 | - | - | - | | 7 | 7 | VDDIO\_1 | DI/DO | GPIO\_3 | 25 | - | - | - | | 7 | 7 | VDDIO\_1 | DI/DO | GPIO\_3 | 26 | - | M0\_JTAG\_TDI | M0 JTAG Test Data Input | | - | 8 | VDDIO\_1 | DI/DO | GPIO\_4 | 0 | - | - | - | | - | 8 | VDDIO\_1 | DI/DO | GPIO\_4 | 1 | - | SPI\_SS | SPI Slave Select | | - | 8 | VDDIO\_1 | DI/DO | GPIO\_4 | 2 | - | SF2\_CS | SF2 Chip Select | | - | 8 | VDDIO\_1 | DI/DO | GPIO\_4 | 3 | - | I2S\_BCLK | I^2^S Bit Clock | | - | 8 | VDDIO\_1 | DI/DO | GPIO\_4 | 4 | - | - | - | | - | 8 | VDDIO\_1 | DI/DO | GPIO\_4 | 5 | - | I2C0\_SCL | I^2^C 0 Serial Clock | | - | 8 | VDDIO\_1 | DI/DO | GPIO\_4 | 6 | - | I2C1\_SCL | I^2^C 1 Serial Clock | | - | 8 | VDDIO\_1 | DI/DO | GPIO\_4 | 7 | uart\_sig\_4\_sel=0 | UART0\_RTS | UART 0 Request To Send | | - | 8 | VDDIO\_1 | DI/DO | GPIO\_4 | 7 | uart\_sig\_4\_sel=1 | UART0\_CTS | UART 0 Clear To Send | | - | 8 | VDDIO\_1 | DI/DO | GPIO\_4 | 7 | uart\_sig\_4\_sel=2 | UART0\_TXD | UART 0 Transmit Data | | - | 8 | VDDIO\_1 | DI/DO | GPIO\_4 | 7 | uart\_sig\_4\_sel=3 | UART0\_RXD | UART 0 Receive Data | | - | 8 | VDDIO\_1 | DI/DO | GPIO\_4 | 7 | uart\_sig\_4\_sel=4 | UART1\_RTS | UART 1 Request To Send | | - | 8 | VDDIO\_1 | DI/DO | GPIO\_4 | 7 | uart\_sig\_4\_sel=5 | UART1\_CTS | UART 1 Clear To Send | | - | 8 | VDDIO\_1 | DI/DO | GPIO\_4 | 7 | uart\_sig\_4\_sel=6 | UART1\_TXD | UART 1 Transmit Data | | - | 8 | VDDIO\_1 | DI/DO | GPIO\_4 | 7 | uart\_sig\_4\_sel=7 | UART1\_RXD | UART 1 Receive Data | | - | 8 | VDDIO\_1 | DI/DO | GPIO\_4 | 7 | uart\_sig\_4\_sel=8 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | - | 8 | VDDIO\_1 | DI/DO | GPIO\_4 | 7 | uart\_sig\_4\_sel=9 | - | - | | - | 8 | VDDIO\_1 | DI/DO | GPIO\_4 | 7 | uart\_sig\_4\_sel=10 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | - | 8 | VDDIO\_1 | DI/DO | GPIO\_4 | 7 | uart\_sig\_4\_sel=11 | ISO11898\_RXD | CAN (ISO 11898) Receive Data | | - | 8 | VDDIO\_1 | DI/DO | GPIO\_4 | 8 | - | - | - | | - | 8 | VDDIO\_1 | DI/DO | GPIO\_4 | 9 | - | - | - | | - | 8 | VDDIO\_1 | DI/DO | GPIO\_4 | 10 | - | - | - | | - | 8 | VDDIO\_1 | DI/DO | GPIO\_4 | 11 | - | SWGPIO4 | Software GPIO 4 | | - | 8 | VDDIO\_1 | DI/DO | GPIO\_4 | 12 | - | - | - | | - | 8 | VDDIO\_1 | DI/DO | GPIO\_4 | 16 | reg\_pwm1\_io\_sel=0 | PWM0\_CH0P | PWM 0 Channel 0 Positive | | - | 8 | VDDIO\_1 | DI/DO | GPIO\_4 | 16 | reg\_pwm1\_io\_sel=1 | PWM0\_CH2P | PWM 0 Channel 2 Positive | | - | 8 | VDDIO\_1 | DI/DO | GPIO\_4 | 22 | - | DBI\_TypeB\_WRn | Display Bus Interface Type B Write Control (QCC744) | | - | 8 | VDDIO\_1 | DI/DO | GPIO\_4 | 23 | - | DBI\_TypeC\_SCL | Display Bus Interface Type C Serial Clock (QCC744 | | - | 8 | VDDIO\_1 | DI/DO | GPIO\_4 | 24 | - | DISP\_QSPI\_SCL | Display Quad SPI Serial Clock (QCC744) | | - | 8 | VDDIO\_1 | DI/DO | GPIO\_4 | 25 | - | - | - | | - | 8 | VDDIO\_1 | DI/DO | GPIO\_4 | 26 | - | M0\_JTAG\_TMS | M0 JTAG Test Mode Select | | - | 9 | VDDIO\_1 | DI/DO | GPIO\_5 | 0 | - | - | - | | - | 9 | VDDIO\_1 | DI/DO | GPIO\_5 | 1 | - | SPI\_SCLK | SPI Serial Clock | | - | 9 | VDDIO\_1 | DI/DO | GPIO\_5 | 2 | - | SF2\_D1 | SF2 Data 1 | | - | 9 | VDDIO\_1 | DI/DO | GPIO\_5 | 3 | - | I2S\_FS | I^2^S Frame Sync | | - | 9 | VDDIO\_1 | DI/DO | GPIO\_5 | 4 | - | - | - | | - | 9 | VDDIO\_1 | DI/DO | GPIO\_5 | 5 | - | I2C0\_SDA | I^2^C 0 Serial Data | | - | 9 | VDDIO\_1 | DI/DO | GPIO\_5 | 6 | - | I2C1\_SDA | I^2^C 1 Serial Data | | - | 9 | VDDIO\_1 | DI/DO | GPIO\_5 | 7 | uart\_sig\_5\_sel=0 | UART0\_RTS | UART 0 Request To Send | | - | 9 | VDDIO\_1 | DI/DO | GPIO\_5 | 7 | uart\_sig\_5\_sel=1 | UART0\_CTS | UART 0 Clear To Send | | - | 9 | VDDIO\_1 | DI/DO | GPIO\_5 | 7 | uart\_sig\_5\_sel=2 | UART0\_TXD | UART 0 Transmit Data | | - | 9 | VDDIO\_1 | DI/DO | GPIO\_5 | 7 | uart\_sig\_5\_sel=3 | UART0\_RXD | UART 0 Receive Data | | - | 9 | VDDIO\_1 | DI/DO | GPIO\_5 | 7 | uart\_sig\_5\_sel=4 | UART1\_RTS | UART 1 Request To Send | | - | 9 | VDDIO\_1 | DI/DO | GPIO\_5 | 7 | uart\_sig\_5\_sel=5 | UART1\_CTS | UART 1 Clear To Send | | - | 9 | VDDIO\_1 | DI/DO | GPIO\_5 | 7 | uart\_sig\_5\_sel=6 | UART1\_TXD | UART 1 Transmit Data | | - | 9 | VDDIO\_1 | DI/DO | GPIO\_5 | 7 | uart\_sig\_5\_sel=7 | UART1\_RXD | UART 1 Receive Data | | - | 9 | VDDIO\_1 | DI/DO | GPIO\_5 | 7 | uart\_sig\_5\_sel=8 | ISO11898\_TXD | CAN (ISO11898) Transmit Data | | - | 9 | VDDIO\_1 | DI/DO | GPIO\_5 | 7 | uart\_sig\_5\_sel=9 | - | - | | - | 9 | VDDIO\_1 | DI/DO | GPIO\_5 | 7 | uart\_sig\_5\_sel=10 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | - | 9 | VDDIO\_1 | DI/DO | GPIO\_5 | 7 | uart\_sig\_5\_sel=11 | ISO11898\_RXD | CAN (ISO 11898) Receive Data | | - | 9 | VDDIO\_1 | DI/DO | GPIO\_5 | 8 | - | - | - | | - | 9 | VDDIO\_1 | DI/DO | GPIO\_5 | 9 | - | - | - | | - | 9 | VDDIO\_1 | DI/DO | GPIO\_5 | 10 | - | - | - | | - | 9 | VDDIO\_1 | DI/DO | GPIO\_5 | 11 | - | SWGPIO5 | Software GPIO 5 | | - | 9 | VDDIO\_1 | DI/DO | GPIO\_5 | 12 | - | - | - | | - | 9 | VDDIO\_1 | DI/DO | GPIO\_5 | 16 | reg\_pwm1\_io\_sel=0 | PWM0\_CH1P | PWM 0 Channel 1 Positive | | - | 9 | VDDIO\_1 | DI/DO | GPIO\_5 | 16 | reg\_pwm1\_io\_sel=1 | PWM0\_CH2N | PWM 0 Channel 2 Negative | | - | 9 | VDDIO\_1 | DI/DO | GPIO\_5 | 22 | - | DBI\_TypeB\_CSn | Display Bus Interface Type B Chip Select (QCC744) | | - | 9 | VDDIO\_1 | DI/DO | GPIO\_5 | 23 | - | DBI\_TypeC\_CSn | Display Bus Interface Type C Chip Select (QCC744) | | - | 9 | VDDIO\_1 | DI/DO | GPIO\_5 | 24 | - | DISP\_QSPI\_CSn | Display Quad SPI Chip Select (QCC744) | | - | 9 | VDDIO\_1 | DI/DO | GPIO\_5 | 25 | - | - | - | | - | 9 | VDDIO\_1 | DI/DO | GPIO\_5 | 26 | - | M0\_JTAG\_TCK | M0 JTAG Test Clock | | - | 10 | VDDIO\_1 | DI/DO | GPIO\_6 | 0 | - | - | - | | - | 10 | VDDIO\_1 | DI/DO | GPIO\_6 | 1 | - | SPI\_MISO | SPI Master Input, Slave Output | | - | 10 | VDDIO\_1 | DI/DO | GPIO\_6 | 2 | - | SF2\_D2 | SF2 Data 2 | | - | 10 | VDDIO\_1 | DI/DO | GPIO\_6 | 3 | - | I2S\_DI/I2S\_RCLK\_O | I^2^S Data Input/I^2^S Receive Clock Output | | - | 10 | VDDIO\_1 | DI/DO | GPIO\_6 | 4 | - | - | - | | - | 10 | VDDIO\_1 | DI/DO | GPIO\_6 | 5 | - | I2C0\_SCL | I^2^C 0 Serial Clock | | - | 10 | VDDIO\_1 | DI/DO | GPIO\_6 | 6 | - | I2C1\_SCL | I^2^C 1 Serial Clock | | - | 10 | VDDIO\_1 | DI/DO | GPIO\_6 | 7 | uart\_sig\_6\_sel=0 | UART0\_RTS | UART 0 Request To Send | | - | 10 | VDDIO\_1 | DI/DO | GPIO\_6 | 7 | uart\_sig\_6\_sel=1 | UART0\_CTS | UART 0 Clear To Send | | - | 10 | VDDIO\_1 | DI/DO | GPIO\_6 | 7 | uart\_sig\_6\_sel=2 | UART0\_TXD | UART 0 Transmit Data | | - | 10 | VDDIO\_1 | DI/DO | GPIO\_6 | 7 | uart\_sig\_6\_sel=3 | UART0\_RXD | UART 0 Receive Data | | - | 10 | VDDIO\_1 | DI/DO | GPIO\_6 | 7 | uart\_sig\_6\_sel=4 | UART1\_RTS | UART 1 Request To Send | | - | 10 | VDDIO\_1 | DI/DO | GPIO\_6 | 7 | uart\_sig\_6\_sel=5 | UART1\_CTS | UART 1 Clear To Send | | - | 10 | VDDIO\_1 | DI/DO | GPIO\_6 | 7 | uart\_sig\_6\_sel=6 | UART1\_TXD | UART 1 Transmit Data | | - | 10 | VDDIO\_1 | DI/DO | GPIO\_6 | 7 | uart\_sig\_6\_sel=7 | UART1\_RXD | UART 1 Receive Data | | - | 10 | VDDIO\_1 | DI/DO | GPIO\_6 | 7 | uart\_sig\_6\_sel=8 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | - | 10 | VDDIO\_1 | DI/DO | GPIO\_6 | 7 | uart\_sig\_6\_sel=9 | - | - | | - | 10 | VDDIO\_1 | DI/DO | GPIO\_6 | 7 | uart\_sig\_6\_sel=10 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | - | 10 | VDDIO\_1 | DI/DO | GPIO\_6 | 7 | uart\_sig\_6\_sel=11 | ISO11898\_RXD | CAN (ISO 11898) Receive Data | | - | 10 | VDDIO\_1 | DI/DO | GPIO\_6 | 8 | - | - | - | | - | 10 | VDDIO\_1 | DI/DO | GPIO\_6 | 9 | - | - | - | | - | 10 | VDDIO\_1 | DI/DO | GPIO\_6 | 10 | - | - | - | | - | 10 | VDDIO\_1 | DI/DO | GPIO\_6 | 11 | - | SWGPIO6 | Software GPIO 6 | | - | 10 | VDDIO\_1 | DI/DO | GPIO\_6 | 12 | - | - | - | | - | 10 | VDDIO\_1 | DI/DO | GPIO\_6 | 16 | reg\_pwm1\_io\_sel=0 | PWM0\_CH2P | PWM 0 Channel 2 Positive | | - | 10 | VDDIO\_1 | DI/DO | GPIO\_6 | 16 | reg\_pwm1\_io\_sel=1 | PWM0\_CH3P | PWM 0 Channel 3 Positive | | - | 10 | VDDIO\_1 | DI/DO | GPIO\_6 | 22 | - | DBI\_TypeB\_RDn | Display Bus Interface Type B Read Control (QCC744) | | - | 10 | VDDIO\_1 | DI/DO | GPIO\_6 | 23 | - | DBI\_TypeC\_SDA0 | Display Bus Interface Type C Serial Data 0 (QCC744) | | - | 10 | VDDIO\_1 | DI/DO | GPIO\_6 | 24 | - | DISP\_QSPI\_SDA0 | Display Quad SPI Serial Data 0 (QCC744) | | - | 10 | VDDIO\_1 | DI/DO | GPIO\_6 | 25 | - | - | | | - | 10 | VDDIO\_1 | DI/DO | GPIO\_6 | 26 | - | M0\_JTAG\_TDO | M0 JTAG Test Data Out | | - | 11 | VDDIO\_1 | DI/DO | GPIO\_7 | 0 | - | - | - | | - | 11 | VDDIO\_1 | DI/DO | GPIO\_7 | 1 | - | SPI\_MOSI | SPI Master Output, Slave Input | | - | 11 | VDDIO\_1 | DI/DO | GPIO\_7 | 2 | - | SF2\_D0 | SF2 Data 0 | | - | 11 | VDDIO\_1 | DI/DO | GPIO\_7 | 3 | - | I2S\_DO/I2S\_RCLK\_O | I^2^S Data Output/I^2^S Receive Clock
Output | | - | 11 | VDDIO\_1 | DI/DO | GPIO\_7 | 4 | - | - | - | | - | 11 | VDDIO\_1 | DI/DO | GPIO\_7 | 5 | - | I2C0\_SDA | I^2^C 0 Serial Data | | - | 11 | VDDIO\_1 | DI/DO | GPIO\_7 | 6 | - | I2C1\_SDA | I^2^C 1 Serial Data | | - | 11 | VDDIO\_1 | DI/DO | GPIO\_7 | 7 | uart\_sig\_7\_sel=0 | UART0\_RTS | UART 0 Request To Send | | - | 11 | VDDIO\_1 | DI/DO | GPIO\_7 | 7 | uart\_sig\_7\_sel=1 | UART0\_CTS | UART 0 Clear To Send | | - | 11 | VDDIO\_1 | DI/DO | GPIO\_7 | 7 | uart\_sig\_7\_sel=2 | UART0\_TXD | UART 0 Transmit Data | | - | 11 | VDDIO\_1 | DI/DO | GPIO\_7 | 7 | uart\_sig\_7\_sel=3 | UART0\_RXD | UART 0 Receive Data | | - | 11 | VDDIO\_1 | DI/DO | GPIO\_7 | 7 | uart\_sig\_7\_sel=4 | UART1\_RTS | UART 1 Request To Send | | - | 11 | VDDIO\_1 | DI/DO | GPIO\_7 | 7 | uart\_sig\_7\_sel=5 | UART1\_CTS | UART 1 Clear To Send | | - | 11 | VDDIO\_1 | DI/DO | GPIO\_7 | 7 | uart\_sig\_7\_sel=6 | UART1\_TXD | UART 1 Transmit Data | | - | 11 | VDDIO\_1 | DI/DO | GPIO\_7 | 7 | uart\_sig\_7\_sel=7 | UART1\_RXD | UART 1 Receive Data | | - | 11 | VDDIO\_1 | DI/DO | GPIO\_7 | 7 | uart\_sig\_7\_sel=8 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | - | 11 | VDDIO\_1 | DI/DO | GPIO\_7 | 7 | uart\_sig\_7\_sel=9 | - | - | | - | 11 | VDDIO\_1 | DI/DO | GPIO\_7 | 7 | uart\_sig\_7\_sel=10 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | - | 11 | VDDIO\_1 | DI/DO | GPIO\_7 | 7 | uart\_sig\_7\_sel=11 | ISO11898\_RXD | CAN (ISO 11898) Receive Data | | - | 11 | VDDIO\_1 | DI/DO | GPIO\_7 | 8 | - | - | - | | - | 11 | VDDIO\_1 | DI/DO | GPIO\_7 | 9 | - | - | - | | - | 11 | VDDIO\_1 | DI/DO | GPIO\_7 | 10 | - | - | - | | - | 11 | VDDIO\_1 | DI/DO | GPIO\_7 | 11 | - | SWGPIO7 | Software GPIO 7 | | - | 11 | VDDIO\_1 | DI/DO | GPIO\_7 | 12 | - | - | - | | - | 11 | VDDIO\_1 | DI/DO | GPIO\_7 | 16 | reg\_pwm1\_io\_sel=0 | PWM0\_CH3P | PWM 0 Channel 3 Positive | | - | 11 | VDDIO\_1 | DI/DO | GPIO\_7 | 16 | reg\_pwm1\_io\_sel=1 | PWM0\_CH3N | PWM 0 Channel 3 Negative | | - | 11 | VDDIO\_1 | DI/DO | GPIO\_7 | 22 | - | DBI\_TypeB\_DCn | Display Bus Interface Type B Data/Command Control (QCC744) | | - | 11 | VDDIO\_1 | DI/DO | GPIO\_7 | 23 | - | DBI\_TypeC\_DCn | Display Bus Interface Type C Data/Command Control (QCC744) | | - | 11 | VDDIO\_1 | DI/DO | GPIO\_7 | 24 | - | DISP\_QSPI\_SDA1 | Display Quad SPI Serial Data 1 QCC744) | | - | 11 | VDDIO\_1 | DI/DO | GPIO\_7 | 25 | - | - | - | | - | 11 | VDDIO\_1 | DI/DO | GPIO\_7 | 26 | - | M0\_JTAG\_TDI | M0 JTAG Test Data Input | | - | 12 | VDDIO\_1 | DI/DO | GPIO\_8 | 0 | - | - | - | | - | 12 | VDDIO\_1 | DI/DO | GPIO\_8 | 1 | - | SPI\_SS | SPI Slave Select | | - | 12 | VDDIO\_1 | DI/DO | GPIO\_8 | 2 | - | SF2\_CLK | SF2 Clock | | - | 12 | VDDIO\_1 | DI/DO | GPIO\_8 | 3 | - | I2S\_BCLK | I^2^S Bit Clock | | - | 12 | VDDIO\_1 | DI/DO | GPIO\_8 | 4 | - | - | - | | - | 12 | VDDIO\_1 | DI/DO | GPIO\_8 | 5 | - | I2C0\_SCL | I^2^C 0 Serial Clock | | - | 12 | VDDIO\_1 | DI/DO | GPIO\_8 | 6 | - | I2C1\_SCL | I^2^C 1 Serial Clock | | - | 12 | VDDIO\_1 | DI/DO | GPIO\_8 | 7 | uart\_sig\_8\_sel=0 | UART0\_RTS | UART 0 Request To Send | | - | 12 | VDDIO\_1 | DI/DO | GPIO\_8 | 7 | uart\_sig\_8\_sel=1 | UART0\_CTS | UART 0 Clear To Send | | - | 12 | VDDIO\_1 | DI/DO | GPIO\_8 | 7 | uart\_sig\_8\_sel=2 | UART0\_TXD | UART 0 Transmit Data | | - | 12 | VDDIO\_1 | DI/DO | GPIO\_8 | 7 | uart\_sig\_8\_sel=3 | UART0\_RXD | UART 0 Receive Data | | - | 12 | VDDIO\_1 | DI/DO | GPIO\_8 | 7 | uart\_sig\_8\_sel=4 | UART1\_RTS | UART 1 Request To Send | | - | 12 | VDDIO\_1 | DI/DO | GPIO\_8 | 7 | uart\_sig\_8\_sel=5 | UART1\_CTS | UART 1 Clear To Send | | - | 12 | VDDIO\_1 | DI/DO | GPIO\_8 | 7 | uart\_sig\_8\_sel=6 | UART1\_TXD | UART 1 Transmit Data | | - | 12 | VDDIO\_1 | DI/DO | GPIO\_8 | 7 | uart\_sig\_8\_sel=7 | UART1\_RXD | UART 1 Receive Data | | - | 12 | VDDIO\_1 | DI/DO | GPIO\_8 | 7 | uart\_sig\_8\_sel=8 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | - | 12 | VDDIO\_1 | DI/DO | GPIO\_8 | 7 | uart\_sig\_8\_sel=9 | - | - | | - | 12 | VDDIO\_1 | DI/DO | GPIO\_8 | 7 | uart\_sig\_8\_sel=10 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | - | 12 | VDDIO\_1 | DI/DO | GPIO\_8 | 7 | uart\_sig\_8\_sel=11 | ISO11898\_RXD | CAN (ISO 11898) Receive Data | | - | 12 | VDDIO\_1 | DI/DO | GPIO\_8 | 8 | - | - | - | | - | 12 | VDDIO\_1 | DI/DO | GPIO\_8 | 9 | - | - | - | | - | 12 | VDDIO\_1 | DI/DO | GPIO\_8 | 10 | - | - | - | | - | 12 | VDDIO\_1 | DI/DO | GPIO\_8 | 11 | - | SWGPIO8 | Software GPIO 8 | | - | 12 | VDDIO\_1 | DI/DO | GPIO\_8 | 12 | - | - | - | | - | 12 | VDDIO\_1 | DI/DO | GPIO\_8 | 16 | reg\_pwm1\_io\_sel=0 | PWM0\_CH0P | PWM 0 Channel 0 Positive | | - | 12 | VDDIO\_1 | DI/DO | GPIO\_8 | 16 | reg\_pwm1\_io\_sel=1 | PWM0\_CH0P | PWM 0 Channel 0 Positive | | - | 12 | VDDIO\_1 | DI/DO | GPIO\_8 | 22 | - | DBI\_TypeB\_DB0 | Display Bus Interface Type B Data Bit 0 (QCC744) | | - | 12 | VDDIO\_1 | DI/DO | GPIO\_8 | 23 | - | DBI\_TypeC\_SCL | Display Bus Interface Type C Serial Clock (QCC744) | | - | 12 | VDDIO\_1 | DI/DO | GPIO\_8 | 24 | - | DISP\_QSPI\_SDA2 | Display Quad SPI Serial Data 2 (QCC744) | | - | 12 | VDDIO\_1 | DI/DO | GPIO\_8 | 25 | - | - | - | | - | 12 | VDDIO\_1 | DI/DO | GPIO\_8 | 26 | - | M0\_JTAG\_TMS | M0 JTAG Test Mode Select | | 8 | 13 | - | Power, Input | VDDIO1 | - | - | VDDIO1 | 1.8 V/3.3 V power supply of GPIO0 to GPIO19 | | - | 14 | VDDIO\_1 | DI/DO | GPIO\_9 | 0 | - | - | - | | - | 14 | VDDIO\_1 | DI/DO | GPIO\_9 | 1 | - | SPI\_SCLK | SPI Serial Clock | | - | 14 | VDDIO\_1 | DI/DO | GPIO\_9 | 2 | - | SF2\_D3 | SF2 Data 3 | | - | 14 | VDDIO\_1 | DI/DO | GPIO\_9 | 3 | - | I2S\_FS | I^2^S Frame Sync | | - | 14 | VDDIO\_1 | DI/DO | GPIO\_9 | 4 | - | - | - | | - | 14 | VDDIO\_1 | DI/DO | GPIO\_9 | 5 | - | I2C0\_SDA | I^2^C 0 Serial Data | | - | 14 | VDDIO\_1 | DI/DO | GPIO\_9 | 6 | - | I2C1\_SDA | I^2^C 1 Serial Data | | - | 14 | VDDIO\_1 | DI/DO | GPIO\_9 | 7 | uart\_sig\_9\_sel=0 | UART0\_RTS | UART 0 Request To Send | | - | 14 | VDDIO\_1 | DI/DO | GPIO\_9 | 7 | uart\_sig\_9\_sel=1 | UART0\_CTS | UART 0 Clear To Send | | - | 14 | VDDIO\_1 | DI/DO | GPIO\_9 | 7 | uart\_sig\_9\_sel=2 | UART0\_TXD | UART 0 Transmit Data | | - | 14 | VDDIO\_1 | DI/DO | GPIO\_9 | 7 | uart\_sig\_9\_sel=3 | UART0\_RXD | UART 0 Receive Data | | - | 14 | VDDIO\_1 | DI/DO | GPIO\_9 | 7 | uart\_sig\_9\_sel=4 | UART1\_RTS | UART 1 Request To Send | | - | 14 | VDDIO\_1 | DI/DO | GPIO\_9 | 7 | uart\_sig\_9\_sel=5 | UART1\_CTS | UART 1 Clear To Send | | - | 14 | VDDIO\_1 | DI/DO | GPIO\_9 | 7 | uart\_sig\_9\_sel=6 | UART1\_TXD | UART 1 Transmit Data | | - | 14 | VDDIO\_1 | DI/DO | GPIO\_9 | 7 | uart\_sig\_9\_sel=7 | UART1\_RXD | UART 1 Receive Data | | - | 14 | VDDIO\_1 | DI/DO | GPIO\_9 | 7 | uart\_sig\_9\_sel=8 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | - | 14 | VDDIO\_1 | DI/DO | GPIO\_9 | 7 | uart\_sig\_9\_sel=9 | - | - | | - | 14 | VDDIO\_1 | DI/DO | GPIO\_9 | 7 | uart\_sig\_9\_sel=10 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | - | 14 | VDDIO\_1 | DI/DO | GPIO\_9 | 7 | uart\_sig\_9\_sel=11 | ISO11898\_RXD | CAN (ISO 11898) Receive Data | | - | 14 | VDDIO\_1 | DI/DO | GPIO\_9 | 8 | - | - | - | | - | 14 | VDDIO\_1 | DI/DO | GPIO\_9 | 9 | - | - | - | | - | 14 | VDDIO\_1 | DI/DO | GPIO\_9 | 10 | - | - | - | | - | 14 | VDDIO\_1 | DI/DO | GPIO\_9 | 11 | - | SWGPIO9 | Software GPIO 9 | | - | 14 | VDDIO\_1 | DI/DO | GPIO\_9 | 12 | - | - | - | | - | 14 | VDDIO\_1 | DI/DO | GPIO\_9 | 16 | reg\_pwm1\_io\_sel=0 | PWM0\_CH1P | PWM 0 Channel 1 Positive | | - | 14 | VDDIO\_1 | DI/DO | GPIO\_9 | 16 | reg\_pwm1\_io\_sel=1 | PWM0\_CH0N | PWM 0 Channel 0 Negative | | - | 14 | VDDIO\_1 | DI/DO | GPIO\_9 | 22 | - | DBI\_TypeB\_DB1 | Display Bus Interface Type B Data Bit 1 (QCC744) | | - | 14 | VDDIO\_1 | DI/DO | GPIO\_9 | 23 | - | DBI\_TypeC\_CSn | Display Bus Interface Type C Chip Select (QCC744) | | - | 14 | VDDIO\_1 | DI/DO | GPIO\_9 | 24 | - | DISP\_QSPI\_SDA3 | Display Quad SPI Serial Data 3 (QCC744) | | - | 14 | VDDIO\_1 | DI/DO | GPIO\_9 | 25 | - | - | - | | - | 14 | VDDIO\_1 | DI/DO | GPIO\_9 | 26 | - | M0\_JTAG\_TCK | M0 JTAG Test Clock | | 9 | 15 | VDDIO\_1 | DI/DO | GPIO\_10 | 0 | - | SDH\_DAT1 | SD Host Data 1 | | 9 | 15 | VDDIO\_1 | DI/DO | GPIO\_10 | 1 | - | SPI\_MISO | SPI Master Input, Slave Output | | 9 | 15 | VDDIO\_1 | DI/DO | GPIO\_10 | 2 | - | SF3\_D3 | SF3 Data 3 | | 9 | 15 | VDDIO\_1 | DI/DO | GPIO\_10 | 3 | - | I2S\_DI/I2S\_RCLK\_O | I^2^S Data Input/I^2^S Receive Clock Output | | 9 | 15 | VDDIO\_1 | DI/DO | GPIO\_10 | 4 | - | - | - | | 9 | 15 | VDDIO\_1 | DI/DO | GPIO\_10 | 5 | - | I2C0\_SCL | I^2^C 0 Serial Clock | | 9 | 15 | VDDIO\_1 | DI/DO | GPIO\_10 | 6 | - | I2C1\_SCL | I^2^C 1 Serial Clock | | 9 | 15 | VDDIO\_1 | DI/DO | GPIO\_10 | 7 | uart\_sig\_10\_sel=0 | UART0\_RTS | UART 0 Request To Send | | 9 | 15 | VDDIO\_1 | DI/DO | GPIO\_10 | 7 | uart\_sig\_10\_sel=1 | UART0\_CTS | UART 0 Clear To Send | | 9 | 15 | VDDIO\_1 | DI/DO | GPIO\_10 | 7 | uart\_sig\_10\_sel=2 | UART0\_TXD | UART 0 Transmit Data | | 9 | 15 | VDDIO\_1 | DI/DO | GPIO\_10 | 7 | uart\_sig\_10\_sel=3 | UART0\_RXD | UART 0 Receive Data | | 9 | 15 | VDDIO\_1 | DI/DO | GPIO\_10 | 7 | uart\_sig\_10\_sel=4 | UART1\_RTS | UART 1 Request To Send | | 9 | 15 | VDDIO\_1 | DI/DO | GPIO\_10 | 7 | uart\_sig\_10\_sel=5 | UART1\_CTS | UART 1 Clear To Send | | 9 | 15 | VDDIO\_1 | DI/DO | GPIO\_10 | 7 | uart\_sig\_10\_sel=6 | UART1\_TXD | UART 1 Transmit Data | | 9 | 15 | VDDIO\_1 | DI/DO | GPIO\_10 | 7 | uart\_sig\_10\_sel=7 | UART1\_RXD | UART 1 Receive Data | | 9 | 15 | VDDIO\_1 | DI/DO | GPIO\_10 | 7 | uart\_sig\_10\_sel=8 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 9 | 15 | VDDIO\_1 | DI/DO | GPIO\_10 | 7 | uart\_sig\_10\_sel=9 | - | - | | 9 | 15 | VDDIO\_1 | DI/DO | GPIO\_10 | 7 | uart\_sig\_10\_sel=10 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 9 | 15 | VDDIO\_1 | DI/DO | GPIO\_10 | 7 | uart\_sig\_10\_sel=11 | ISO11898\_RXD | CAN (ISO 11898) Receive Data | | 9 | 15 | VDDIO\_1 | DI/DO | GPIO\_10 | 8 | - | - | - | | 9 | 15 | VDDIO\_1 | DI/DO | GPIO\_10 | 9 | - | CAM1\_DAT1 | Camera 1 Data 1 (QCC744) | | 9 | 15 | VDDIO\_1 | DI/DO | GPIO\_10 | 10 | - | ADC\_CH7 | ADC Channel 7 | | 9 | 15 | VDDIO\_1 | DI/DO | GPIO\_10 | 11 | - | SWGPIO10 | Software GPIO 10 | | 9 | 15 | VDDIO\_1 | DI/DO | GPIO\_10 | 12 | - | SDIO\_DAT2 | SDIO Data 2 | | 9 | 15 | VDDIO\_1 | DI/DO | GPIO\_10 | 16 | reg\_pwm1\_io\_sel=0 | PWM0\_CH2P | PWM 0 Channel 2 Positive | | 9 | 15 | VDDIO\_1 | DI/DO | GPIO\_10 | 16 | reg\_pwm1\_io\_sel=1 | PWM0\_CH1P | PWM 0 Channel 1 Positive | | 9 | 15 | VDDIO\_1 | DI/DO | GPIO\_10 | 22 | - | DBI\_TypeB\_DB2 | Display Bus Interface Type B Data Bit 2 (QCC744) | | 9 | 15 | VDDIO\_1 | DI/DO | GPIO\_10 | 23 | - | DBI\_TypeC\_SDA0 | Display Bus Interface Type C Serial Data 0 (QCC744) | | 9 | 15 | VDDIO\_1 | DI/DO | GPIO\_10 | 24 | - | DISP\_QSPI\_SCL | Display Quad SPI Serial Clock (QCC744) | | 9 | 15 | VDDIO\_1 | DI/DO | GPIO\_10 | 25 | - | - | | | 9 | 15 | VDDIO\_1 | DI/DO | GPIO\_10 | 26 | - | M0\_JTAG\_TDO | M0 JTAG Test Data Out | | 10 | 16 | VDDIO\_1 | DI/DO | GPIO\_11 | 0 | | SDH\_DAT0 | SD Host Data 0 | | 10 | 16 | VDDIO\_1 | DI/DO | GPIO\_11 | 1 | - | SPI\_MOSI | SPI Master Output, Slave Input | | 10 | 16 | VDDIO\_1 | DI/DO | GPIO\_11 | 2 | - | SF3\_CLK | SF3 Clock | | 10 | 16 | VDDIO\_1 | DI/DO | GPIO\_11 | 3 | - | I2S\_DO/I2S\_RCLK\_O | I^2^S Data Output/I^2^S Receive Clock
Output | | 10 | 16 | VDDIO\_1 | DI/DO | GPIO\_11 | 4 | - | - | - | | 10 | 16 | VDDIO\_1 | DI/DO | GPIO\_11 | 5 | - | I2C0\_SDA | I^2^C 0 Serial Data | | 10 | 16 | VDDIO\_1 | DI/DO | GPIO\_11 | 6 | - | I2C1\_SDA | I^2^C 1 Serial Data | | 10 | 16 | VDDIO\_1 | DI/DO | GPIO\_11 | 7 | uart\_sig\_11\_sel=0 | UART0\_RTS | UART 0 Request To Send | | 10 | 16 | VDDIO\_1 | DI/DO | GPIO\_11 | 7 | uart\_sig\_11\_sel=1 | UART0\_CTS | UART 0 Clear To Send | | 10 | 16 | VDDIO\_1 | DI/DO | GPIO\_11 | 7 | uart\_sig\_11\_sel=2 | UART0\_TXD | UART 0 Transmit Data | | 10 | 16 | VDDIO\_1 | DI/DO | GPIO\_11 | 7 | uart\_sig\_11\_sel=3 | UART0\_RXD | UART 0 Receive Data | | 10 | 16 | VDDIO\_1 | DI/DO | GPIO\_11 | 7 | uart\_sig\_11\_sel=4 | UART1\_RTS | UART 1 Request To Send | | 10 | 16 | VDDIO\_1 | DI/DO | GPIO\_11 | 7 | uart\_sig\_11\_sel=5 | UART1\_CTS | UART 1 Clear To Send | | 10 | 16 | VDDIO\_1 | DI/DO | GPIO\_11 | 7 | uart\_sig\_11\_sel=6 | UART1\_TXD | UART 1 Transmit Data | | 10 | 16 | VDDIO\_1 | DI/DO | GPIO\_11 | 7 | uart\_sig\_11\_sel=7 | UART1\_RXD | UART 1 Receive Data | | 10 | 16 | VDDIO\_1 | DI/DO | GPIO\_11 | 7 | uart\_sig\_11\_sel=8 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 10 | 16 | VDDIO\_1 | DI/DO | GPIO\_11 | 7 | uart\_sig\_11\_sel=9 | - | - | | 10 | 16 | VDDIO\_1 | DI/DO | GPIO\_11 | 7 | uart\_sig\_11\_sel=10 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 10 | 16 | VDDIO\_1 | DI/DO | GPIO\_11 | 7 | uart\_sig\_11\_sel=11 | ISO11898\_RXD | CAN (ISO 11898) Receive Data | | 10 | 16 | VDDIO\_1 | DI/DO | GPIO\_11 | 8 | - | - | - | | 10 | 16 | VDDIO\_1 | DI/DO | GPIO\_11 | 9 | - | CAM1\_DAT2 | Camera 1 Data 2 (QCC744) | | 10 | 16 | VDDIO\_1 | DI/DO | GPIO\_11 | 10 | - | - | - | | 10 | 16 | VDDIO\_1 | DI/DO | GPIO\_11 | 11 | - | SWGPIO11 | Software GPIO 11 | | 10 | 16 | VDDIO\_1 | DI/DO | GPIO\_11 | 12 | - | SDIO\_DAT3 | SDIO Data 3 | | 10 | 16 | VDDIO\_1 | DI/DO | GPIO\_11 | 16 | reg\_pwm1\_io\_sel=0 | PWM0\_CH3P | PWM 0 Channel 3 Positive | | 10 | 16 | VDDIO\_1 | DI/DO | GPIO\_11 | 16 | reg\_pwm1\_io\_sel=1 | PWM0\_CH1N | PWM 0 Channel 1 Negative | | 10 | 16 | VDDIO\_1 | DI/DO | GPIO\_11 | 22 | - | DBI\_TypeB\_DB3 | Display Bus Interface Type B Data Bit 3 (QCC744) | | 10 | 16 | VDDIO\_1 | DI/DO | GPIO\_11 | 23 | - | DBI\_TypeC\_DCn | Display Bus Interface Type C Data/Command Control (QCC744) | | 10 | 16 | VDDIO\_1 | DI/DO | GPIO\_11 | 24 | - | DISP\_QSPI\_CSn | Display Quad SPI Chip Select (QCC744) | | 10 | 16 | VDDIO\_1 | DI/DO | GPIO\_11 | 25 | - | - | - | | 10 | 16 | VDDIO\_1 | DI/DO | GPIO\_11 | 26 | - | M0\_JTAG\_TDI | M0 JTAG Test Data Input | | 11 | 17 | VDDIO\_1 | DI/DO | GPIO\_12 | 0 | | SDH\_CLK | SD Host Clock | | 11 | 17 | VDDIO\_1 | DI/DO | GPIO\_12 | 1 | - | SPI\_SS | SPI Slave Select | | 11 | 17 | VDDIO\_1 | DI/DO | GPIO\_12 | 2 | - | SF3\_D0 | SF3 Data0 | | 11 | 17 | VDDIO\_1 | DI/DO | GPIO\_12 | 3 | - | I2S\_BCLK | I^2^S Bit Clock | | 11 | 17 | VDDIO\_1 | DI/DO | GPIO\_12 | 4 | - | - | - | | 11 | 17 | VDDIO\_1 | DI/DO | GPIO\_12 | 5 | - | I2C0\_SCL | I^2^C 0 Serial Clock | | 11 | 17 | VDDIO\_1 | DI/DO | GPIO\_12 | 6 | - | I2C1\_SCL | I^2^C 1 Serial Clock | | 11 | 17 | VDDIO\_1 | DI/DO | GPIO\_12 | 7 | uart\_sig\_0\_sel=0 | UART0\_RTS | UART 0 Request To Send | | 11 | 17 | VDDIO\_1 | DI/DO | GPIO\_12 | 7 | uart\_sig\_0\_sel=1 | UART0\_CTS | UART 0 Clear To Send | | 11 | 17 | VDDIO\_1 | DI/DO | GPIO\_12 | 7 | uart\_sig\_0\_sel=2 | UART0\_TXD | UART 0 Transmit Data | | 11 | 17 | VDDIO\_1 | DI/DO | GPIO\_12 | 7 | uart\_sig\_0\_sel=3 | UART0\_RXD | UART 0 Receive Data | | 11 | 17 | VDDIO\_1 | DI/DO | GPIO\_12 | 7 | uart\_sig\_0\_sel=4 | UART1\_RTS | UART 1 Request To Send | | 11 | 17 | VDDIO\_1 | DI/DO | GPIO\_12 | 7 | uart\_sig\_0\_sel=5 | UART1\_CTS | UART 1 Clear To Send | | 11 | 17 | VDDIO\_1 | DI/DO | GPIO\_12 | 7 | uart\_sig\_0\_sel=6 | UART1\_TXD | UART 1 Transmit Data | | 11 | 17 | VDDIO\_1 | DI/DO | GPIO\_12 | 7 | uart\_sig\_0\_sel=7 | UART1\_RXD | UART 1 Receive Data | | 11 | 17 | VDDIO\_1 | DI/DO | GPIO\_12 | 7 | uart\_sig\_0\_sel=8 | ISO11898\_TXD | CAN (ISO11898) Transmit Data | | 11 | 17 | VDDIO\_1 | DI/DO | GPIO\_12 | 7 | uart\_sig\_0\_sel=9 | - | - | | 11 | 17 | VDDIO\_1 | DI/DO | GPIO\_12 | 7 | uart\_sig\_0\_sel=10 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 11 | 17 | VDDIO\_1 | DI/DO | GPIO\_12 | 7 | uart\_sig\_0\_sel=11 | ISO11898\_RXD | CAN (ISO 11898) Receive Data | | 11 | 17 | VDDIO\_1 | DI/DO | GPIO\_12 | 8 | - | - | - | | 11 | 17 | VDDIO\_1 | DI/DO | GPIO\_12 | 9 | - | CAM1\_DAT3 | Camera 1 Data 3 (QCC744) | | 11 | 17 | VDDIO\_1 | DI/DO | GPIO\_12 | 10 | - | ADC\_CH6 | ADC Channel 6 | | 11 | 17 | VDDIO\_1 | DI/DO | GPIO\_12 | 11 | - | SWGPIO12 | Software GPIO 12 | | 11 | 17 | VDDIO\_1 | DI/DO | GPIO\_12 | 12 | - | SDIO\_CMD | SDIO Command | | 11 | 17 | VDDIO\_1 | DI/DO | GPIO\_12 | 16 | reg\_pwm1\_io\_sel=0 | PWM0\_CH0P | PWM 0 Channel 0 Positive | | 11 | 17 | VDDIO\_1 | DI/DO | GPIO\_12 | 16 | reg\_pwm1\_io\_sel=1 | PWM0\_CH2P | PWM 0 Channel 2 Positive | | 11 | 17 | VDDIO\_1 | DI/DO | GPIO\_12 | 22 | - | DBI\_TypeB\_DB4 | Display Bus Interface Type B Data Bit 4 (QCC744) | | 11 | 17 | VDDIO\_1 | DI/DO | GPIO\_12 | 23 | - | DBI\_TypeC\_SCL | Display Bus Interface Type C Serial Clock (QCC744) | | 11 | 17 | VDDIO\_1 | DI/DO | GPIO\_12 | 24 | - | DISP\_QSPI\_SDA0 | Display Quad SPI Serial Data 0 (QCC744) | | 11 | 17 | VDDIO\_1 | DI/DO | GPIO\_12 | 25 | - | - | - | | 11 | 17 | VDDIO\_1 | DI/DO | GPIO\_12 | 26 | - | M0\_JTAG\_TMS | M0 JTAG Test Mode Select | | 12 | 18 | VDDIO\_1 | DI/DO | GPIO\_13 | 0 | - | SDH\_CMD | SD Host Command | | 12 | 18 | VDDIO\_1 | DI/DO | GPIO\_13 | 1 | - | SPI\_SCLK | SPI Serial Clock | | 12 | 18 | VDDIO\_1 | DI/DO | GPIO\_13 | 2 | - | SF3\_D2 | SF3 Data2 | | 12 | 18 | VDDIO\_1 | DI/DO | GPIO\_13 | 3 | - | I2S\_FS | I^2^S Frame Sync | | 12 | 18 | VDDIO\_1 | DI/DO | GPIO\_13 | 4 | - | - | - | | 12 | 18 | VDDIO\_1 | DI/DO | GPIO\_13 | 5 | - | I2C0\_SDA | I^2^C 0 Serial Data | | 12 | 18 | VDDIO\_1 | DI/DO | GPIO\_13 | 6 | - | I2C1\_SDA | I^2^C 1 Serial Data | | 12 | 18 | VDDIO\_1 | DI/DO | GPIO\_13 | 7 | uart\_sig\_1\_sel=0 | UART0\_RTS | UART 0 Request To Send | | 12 | 18 | VDDIO\_1 | DI/DO | GPIO\_13 | 7 | uart\_sig\_1\_sel=1 | UART0\_CTS | UART 0 Clear To Send | | 12 | 18 | VDDIO\_1 | DI/DO | GPIO\_13 | 7 | uart\_sig\_1\_sel=2 | UART0\_TXD | UART 0 Transmit Data | | 12 | 18 | VDDIO\_1 | DI/DO | GPIO\_13 | 7 | uart\_sig\_1\_sel=3 | UART0\_RXD | UART 0 Receive Data | | 12 | 18 | VDDIO\_1 | DI/DO | GPIO\_13 | 7 | uart\_sig\_1\_sel=4 | UART1\_RTS | UART 1 Request To Send | | 12 | 18 | VDDIO\_1 | DI/DO | GPIO\_13 | 7 | uart\_sig\_1\_sel=5 | UART1\_CTS | UART 1 Clear To Send | | 12 | 18 | VDDIO\_1 | DI/DO | GPIO\_13 | 7 | uart\_sig\_1\_sel=6 | UART1\_TXD | UART 1 Transmit Data | | 12 | 18 | VDDIO\_1 | DI/DO | GPIO\_13 | 7 | uart\_sig\_1\_sel=7 | UART1\_RXD | UART 1 Receive Data | | 12 | 18 | VDDIO\_1 | DI/DO | GPIO\_13 | 7 | uart\_sig\_1\_sel=8 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 12 | 18 | VDDIO\_1 | DI/DO | GPIO\_13 | 7 | uart\_sig\_1\_sel=9 | - | - | | 12 | 18 | VDDIO\_1 | DI/DO | GPIO\_13 | 7 | uart\_sig\_1\_sel=10 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 12 | 18 | VDDIO\_1 | DI/DO | GPIO\_13 | 7 | uart\_sig\_1\_sel=11 | ISO11898\_RXD | CAN (ISO 11898) Receive Data | | 12 | 18 | VDDIO\_1 | DI/DO | GPIO\_13 | 8 | - | - | - | | 12 | 18 | VDDIO\_1 | DI/DO | GPIO\_13 | 9 | - | CAM1\_CLK | Camera 1 Clock (QCC744) | | 12 | 18 | VDDIO\_1 | DI/DO | GPIO\_13 | 10 | - | ADC\_CH5 | ADC Channel 5 | | 12 | 18 | VDDIO\_1 | DI/DO | GPIO\_13 | 11 | - | SWGPIO13 | Software GPIO 13 | | 12 | 18 | VDDIO\_1 | DI/DO | GPIO\_13 | 12 | - | SDIO\_CLK | SDIO Clock | | 12 | 18 | VDDIO\_1 | DI/DO | GPIO\_13 | 16 | reg\_pwm1\_io\_sel=0 | PWM0\_CH1P | PWM 0 Channel 1 Positive | | 12 | 18 | VDDIO\_1 | DI/DO | GPIO\_13 | 16 | reg\_pwm1\_io\_sel=1 | PWM0\_CH2N | PWM 0 Channel 2 Negative | | 12 | 18 | VDDIO\_1 | DI/DO | GPIO\_13 | 22 | - | DBI\_TypeB\_DB5 | Display Bus Interface Type B Data Bit 5 (QCC744) | | 12 | 18 | VDDIO\_1 | DI/DO | GPIO\_13 | 23 | - | DBI\_TypeC\_CSn | Display Bus Interface Type C Chip Select (QCC744) | | 12 | 18 | VDDIO\_1 | DI/DO | GPIO\_13 | 24 | - | DISP\_QSPI\_SDA1 | Display Quad SPI Serial Data 1 (QCC744) | | 12 | 18 | VDDIO\_1 | DI/DO | GPIO\_13 | 25 | - | - | - | | 12 | 18 | VDDIO\_1 | DI/DO | GPIO\_13 | 26 | - | M0\_JTAG\_TCK | M0 JTAG Test Clock | | 13 | 19 | VDDIO\_1 | DI/DO | GPIO\_14 | 0 | | SDH\_DAT3 | SD Host Data 3 | | 13 | 19 | VDDIO\_1 | DI/DO | GPIO\_14 | 1 | - | SPI\_MISO | SPI Master Input, Slave Output | | 13 | 19 | VDDIO\_1 | DI/DO | GPIO\_14 | 2 | - | SF3\_D1 | SF3 Data 1 | | 13 | 19 | VDDIO\_1 | DI/DO | GPIO\_14 | 3 | - | I2S\_DI/I2S\_RCLK\_O | I^2^S Data Input/I^2^S Receive Clock Output | | 13 | 19 | VDDIO\_1 | DI/DO | GPIO\_14 | 4 | - | - | - | | 13 | 19 | VDDIO\_1 | DI/DO | GPIO\_14 | 5 | - | I2C0\_SCL | I^2^C 0 Serial Clock | | 13 | 19 | VDDIO\_1 | DI/DO | GPIO\_14 | 6 | - | I2C1\_SCL | I^2^C 1 Serial Clock | | 13 | 19 | VDDIO\_1 | DI/DO | GPIO\_14 | 7 | uart\_sig\_2\_sel=0 | UART0\_RTS | UART 0 Request To Send | | 13 | 19 | VDDIO\_1 | DI/DO | GPIO\_14 | 7 | uart\_sig\_2\_sel=1 | UART0\_CTS | UART 0 Clear To Send | | 13 | 19 | VDDIO\_1 | DI/DO | GPIO\_14 | 7 | uart\_sig\_2\_sel=2 | UART0\_TXD | UART 0 Transmit Data | | 13 | 19 | VDDIO\_1 | DI/DO | GPIO\_14 | 7 | uart\_sig\_2\_sel=3 | UART0\_RXD | UART 0 Receive Data | | 13 | 19 | VDDIO\_1 | DI/DO | GPIO\_14 | 7 | uart\_sig\_2\_sel=4 | UART1\_RTS | UART 1 Request To Send | | 13 | 19 | VDDIO\_1 | DI/DO | GPIO\_14 | 7 | uart\_sig\_2\_sel=5 | UART1\_CTS | UART 1 Clear To Send | | 13 | 19 | VDDIO\_1 | DI/DO | GPIO\_14 | 7 | uart\_sig\_2\_sel=6 | UART1\_TXD | UART 1 Transmit Data | | 13 | 19 | VDDIO\_1 | DI/DO | GPIO\_14 | 7 | uart\_sig\_2\_sel=7 | UART1\_RXD | UART 1 Receive Data | | 13 | 19 | VDDIO\_1 | DI/DO | GPIO\_14 | 7 | uart\_sig\_2\_sel=8 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 13 | 19 | VDDIO\_1 | DI/DO | GPIO\_14 | 7 | uart\_sig\_2\_sel=9 | - | - | | 13 | 19 | VDDIO\_1 | DI/DO | GPIO\_14 | 7 | uart\_sig\_2\_sel=10 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 13 | 19 | VDDIO\_1 | DI/DO | GPIO\_14 | 7 | uart\_sig\_2\_sel=11 | ISO11898\_RXD | CAN (ISO 11898) Receive Data | | 13 | 19 | VDDIO\_1 | DI/DO | GPIO\_14 | 8 | - | - | - | | 13 | 19 | VDDIO\_1 | DI/DO | GPIO\_14 | 9 | - | CAM1\_DAT4 | Camera 1 Data 4 (QCC744) | | 13 | 19 | VDDIO\_1 | DI/DO | GPIO\_14 | 10 | - | ADC\_CH4 | ADC Channel 4 | | 13 | 19 | VDDIO\_1 | DI/DO | GPIO\_14 | 11 | - | SWGPIO14 | Software GPIO 14 | | 13 | 19 | VDDIO\_1 | DI/DO | GPIO\_14 | 12 | - | SDIO\_DAT0 | SDIO Data 0 | | 13 | 19 | VDDIO\_1 | DI/DO | GPIO\_14 | 16 | reg\_pwm1\_io\_sel=0 | PWM0\_CH2P | PWM 0 Channel 2 Positive | | 13 | 19 | VDDIO\_1 | DI/DO | GPIO\_14 | 16 | reg\_pwm1\_io\_sel=1 | PWM0\_CH3P | PWM 0 Channel 3 Positive | | 13 | 19 | VDDIO\_1 | DI/DO | GPIO\_14 | 22 | - | DBI\_TypeB\_DB6 | Display Bus Interface Type B Data Bit 6 (QCC744) | | 13 | 19 | VDDIO\_1 | DI/DO | GPIO\_14 | 23 | - | DBI\_TypeC\_SDA0 | Display Bus Interface Type C Serial Data 0 (QCC744) | | 13 | 19 | VDDIO\_1 | DI/DO | GPIO\_14 | 24 | - | DISP\_QSPI\_SDA2 | Display Quad SPI Serial Data 2 (QCC744) | | 13 | 19 | VDDIO\_1 | DI/DO | GPIO\_14 | 25 | - | AUDAC\_PWM\_P | AUDAC\_PWM\_P | | 13 | 19 | VDDIO\_1 | DI/DO | GPIO\_14 | 26 | - | M0\_JTAG\_TDO | M0 JTAG Test Data Out | | 14 | 20 | VDDIO\_1 | DI/DO | GPIO\_15 | 0 | | SDH\_DAT2 | SD Host Data 2 | | 14 | 20 | VDDIO\_1 | DI/DO | GPIO\_15 | 1 | - | SPI\_MOSI | SPI Master Output, Slave Input | | 14 | 20 | VDDIO\_1 | DI/DO | GPIO\_15 | 2 | - | SF3\_CS | SF3 Chip Select | | 14 | 20 | VDDIO\_1 | DI/DO | GPIO\_15 | 3 | - | I2S\_DO/I2S\_RCLK\_O | I^2^S Data Output/I^2^S Receive Clock
Output | | 14 | 20 | VDDIO\_1 | DI/DO | GPIO\_15 | 4 | - | - | - | | 14 | 20 | VDDIO\_1 | DI/DO | GPIO\_15 | 5 | - | I2C0\_SDA | I^2^C 0 Serial Data | | 14 | 20 | VDDIO\_1 | DI/DO | GPIO\_15 | 6 | - | I2C1\_SDA | I^2^C 1 Serial Data | | 14 | 20 | VDDIO\_1 | DI/DO | GPIO\_15 | 7 | uart\_sig\_3\_sel=0 | UART0\_RTS | UART 0 Request To Send | | 14 | 20 | VDDIO\_1 | DI/DO | GPIO\_15 | 7 | uart\_sig\_3\_sel=1 | UART0\_CTS | UART 0 Clear To Send | | 14 | 20 | VDDIO\_1 | DI/DO | GPIO\_15 | 7 | uart\_sig\_3\_sel=2 | UART0\_TXD | UART 0 Transmit Data | | 14 | 20 | VDDIO\_1 | DI/DO | GPIO\_15 | 7 | uart\_sig\_3\_sel=3 | UART0\_RXD | UART 0 Receive Data | | 14 | 20 | VDDIO\_1 | DI/DO | GPIO\_15 | 7 | uart\_sig\_3\_sel=4 | UART1\_RTS | UART 1 Request To Send | | 14 | 20 | VDDIO\_1 | DI/DO | GPIO\_15 | 7 | uart\_sig\_3\_sel=5 | UART1\_CTS | UART 1 Clear To Send | | 14 | 20 | VDDIO\_1 | DI/DO | GPIO\_15 | 7 | uart\_sig\_3\_sel=6 | UART1\_TXD | UART 1 Transmit Data | | 14 | 20 | VDDIO\_1 | DI/DO | GPIO\_15 | 7 | uart\_sig\_3\_sel=7 | UART1\_RXD | UART 1 Receive Data | | 14 | 20 | VDDIO\_1 | DI/DO | GPIO\_15 | 7 | uart\_sig\_3\_sel=8 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 14 | 20 | VDDIO\_1 | DI/DO | GPIO\_15 | 7 | uart\_sig\_3\_sel=9 | - | - | | 14 | 20 | VDDIO\_1 | DI/DO | GPIO\_15 | 7 | uart\_sig\_3\_sel=10 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 14 | 20 | VDDIO\_1 | DI/DO | GPIO\_15 | 7 | uart\_sig\_3\_sel=11 | ISO11898\_RXD | CAN (ISO 11898) Receive Data | | 14 | 20 | VDDIO\_1 | DI/DO | GPIO\_15 | 8 | - | - | - | | 14 | 20 | VDDIO\_1 | DI/DO | GPIO\_15 | 9 | - | CAM1\_DAT5 | Camera 1 Data 5 (QCC744) | | 14 | 20 | VDDIO\_1 | DI/DO | GPIO\_15 | 10 | - | - | - | | 14 | 20 | VDDIO\_1 | DI/DO | GPIO\_15 | 11 | - | SWGPIO15 | Software GPIO 15 | | 14 | 20 | VDDIO\_1 | DI/DO | GPIO\_15 | 12 | - | SDIO\_DAT1 | SDIO Data 1 | | 14 | 20 | VDDIO\_1 | DI/DO | GPIO\_15 | 16 | reg\_pwm1\_io\_sel=0 | PWM0\_CH3P | PWM 0 Channel 3 Positive | | 14 | 20 | VDDIO\_1 | DI/DO | GPIO\_15 | 16 | reg\_pwm1\_io\_sel=1 | PWM0\_CH3N | PWM 0 Channel 3 Negative | | 14 | 20 | VDDIO\_1 | DI/DO | GPIO\_15 | 22 | - | DBI\_TypeB\_DB7 | Display Bus Interface Type B Data Bit 7 (QCC744) | | 14 | 20 | VDDIO\_1 | DI/DO | GPIO\_15 | 23 | - | DBI\_TypeC\_DCn | Display Bus Interface Type C Data/Command Control (QCC744) | | 14 | 20 | VDDIO\_1 | DI/DO | GPIO\_15 | 24 | - | DISP\_QSPI\_SDA3 | Display Quad SPI Serial Data 3 (QCC744) | | 14 | 20 | VDDIO\_1 | DI/DO | GPIO\_15 | 25 | - | AUDAC\_PWM\_N | AUDAC\_PWM\_N | | 14 | 20 | VDDIO\_1 | DI/DO | GPIO\_15 | 26 | - | M0\_JTAG\_TDI | M0 JTAG Test Data Input | | 15 | 21 | AVDD33\_AON | DI/DO | GPIO\_16 | - | - | - | - | | 15 | 21 | AVDD33\_AON | DI/DO | GPIO\_16 | 1 | - | SPI\_SS | SPI Slave Select | | 15 | 21 | AVDD33\_AON | DI/DO | GPIO\_16 | 2 | - | - | - | | 15 | 21 | AVDD33\_AON | DI/DO | GPIO\_16 | 3 | - | I2S\_BCLK | I^2^S Bit Clock | | 15 | 21 | AVDD33\_AON | DI/DO | GPIO\_16 | 4 | - | - | - | | 15 | 21 | AVDD33\_AON | DI/DO | GPIO\_16 | 5 | - | I2C0\_SCL | I^2^C 0 Serial Clock | | 15 | 21 | AVDD33\_AON | DI/DO | GPIO\_16 | 6 | - | I2C1\_SCL | I^2^C 1 Serial Clock | | 15 | 21 | AVDD33\_AON | DI/DO | GPIO\_16 | 7 | uart\_sig\_4\_sel=0 | UART0\_RTS | UART 0 Request To Send | | 15 | 21 | AVDD33\_AON | DI/DO | GPIO\_16 | 7 | uart\_sig\_4\_sel=1 | UART0\_CTS | UART 0 Clear To Send | | 15 | 21 | AVDD33\_AON | DI/DO | GPIO\_16 | 7 | uart\_sig\_4\_sel=2 | UART0\_TXD | UART 0 Transmit Data | | 15 | 21 | AVDD33\_AON | DI/DO | GPIO\_16 | 7 | uart\_sig\_4\_sel=3 | UART0\_RXD | UART 0 Receive Data | | 15 | 21 | AVDD33\_AON | DI/DO | GPIO\_16 | 7 | uart\_sig\_4\_sel=4 | UART1\_RTS | UART 1 Request To Send | | 15 | 21 | AVDD33\_AON | DI/DO | GPIO\_16 | 7 | uart\_sig\_4\_sel=5 | UART1\_CTS | UART 1 Clear To Send | | 15 | 21 | AVDD33\_AON | DI/DO | GPIO\_16 | 7 | uart\_sig\_4\_sel=6 | UART1\_TXD | UART 1 Transmit Data | | 15 | 21 | AVDD33\_AON | DI/DO | GPIO\_16 | 7 | uart\_sig\_4\_sel=7 | UART1\_RXD | UART 1 Receive Data | | 15 | 21 | AVDD33\_AON | DI/DO | GPIO\_16 | 7 | uart\_sig\_4\_sel=8 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 15 | 21 | AVDD33\_AON | DI/DO | GPIO\_16 | 7 | uart\_sig\_4\_sel=9 | - | - | | 15 | 21 | AVDD33\_AON | DI/DO | GPIO\_16 | 7 | uart\_sig\_4\_sel=10 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 15 | 21 | AVDD33\_AON | DI/DO | GPIO\_16 | 7 | uart\_sig\_4\_sel=11 | ISO11898\_RXD | CAN (ISO11898) Receive Data | | 15 | 21 | AVDD33\_AON | DI/DO | GPIO\_16 | 8 | - | - | - | | 15 | 21 | AVDD33\_AON | DI/DO | GPIO\_16 | 9 | - | CAM1\_DAT6 | Camera 1 Data 6 (QCC744) | | 15 | 21 | AVDD33\_AON | DI/DO | GPIO\_16 | 10 | - | - | - | | 15 | 21 | AVDD33\_AON | DI/DO | GPIO\_16 | 11 | - | SWGPIO16 | Software GPIO 16 | | 15 | 21 | AVDD33\_AON | DI/DO | GPIO\_16 | 12 | - | - | - | | 15 | 21 | AVDD33\_AON | DI/DO | GPIO\_16 | 16 | reg\_pwm1\_io\_sel=0 | PWM0\_CH0P | PWM 0 Channel 0 Positive | | 15 | 21 | AVDD33\_AON | DI/DO | GPIO\_16 | 16 | reg\_pwm1\_io\_sel=1 | PWM0\_CH0P | PWM 0 Channel 0 Positive | | 15 | 21 | AVDD33\_AON | DI/DO | GPIO\_16 | 22 | - | - | - | | 15 | 21 | AVDD33\_AON | DI/DO | GPIO\_16 | 23 | - | - | - | | 15 | 21 | AVDD33\_AON | DI/DO | GPIO\_16 | 24 | - | - | - | | 15 | 21 | AVDD33\_AON | DI/DO | GPIO\_16 | 25 | - | - | - | | 15 | 21 | AVDD33\_AON | DI/DO | GPIO\_16 | 26 | - | M0\_JTAG\_TMS | M0 JTAG Test Mode Select | | 16 | 22 | AVDD33\_AON | DI/DO | GPIO\_17 | 0 | - | - | - | | 16 | 22 | AVDD33\_AON | DI/DO | GPIO\_17 | 1 | - | SPI\_SCLK | SPI Serial Clock | | 16 | 22 | AVDD33\_AON | DI/DO | GPIO\_17 | 2 | - | - | - | | 16 | 22 | AVDD33\_AON | DI/DO | GPIO\_17 | 3 | - | I2S\_FS | I^2^S Frame Sync | | 16 | 22 | AVDD33\_AON | DI/DO | GPIO\_17 | 4 | - | - | - | | 16 | 22 | AVDD33\_AON | DI/DO | GPIO\_17 | 5 | - | I2C0\_SDA | I^2^C 0 Serial Data | | 16 | 22 | AVDD33\_AON | DI/DO | GPIO\_17 | 6 | - | I2C1\_SDA | I^2^C 1 Serial Data | | 16 | 22 | AVDD33\_AON | DI/DO | GPIO\_17 | 7 | uart\_sig\_5\_sel=0 | UART0\_RTS | UART 0 Request To Send | | 16 | 22 | AVDD33\_AON | DI/DO | GPIO\_17 | 7 | uart\_sig\_5\_sel=1 | UART0\_CTS | UART 0 Clear To Send | | 16 | 22 | AVDD33\_AON | DI/DO | GPIO\_17 | 7 | uart\_sig\_5\_sel=2 | UART0\_TXD | UART 0 Transmit Data | | 16 | 22 | AVDD33\_AON | DI/DO | GPIO\_17 | 7 | uart\_sig\_5\_sel=3 | UART0\_RXD | UART 0 Receive Data | | 16 | 22 | AVDD33\_AON | DI/DO | GPIO\_17 | 7 | uart\_sig\_5\_sel=4 | UART1\_RTS | UART 1 Request To Send | | 16 | 22 | AVDD33\_AON | DI/DO | GPIO\_17 | 7 | uart\_sig\_5\_sel=5 | UART1\_CTS | UART 1 Clear To Send | | 16 | 22 | AVDD33\_AON | DI/DO | GPIO\_17 | 7 | uart\_sig\_5\_sel=6 | UART1\_TXD | UART 1 Transmit Data | | 16 | 22 | AVDD33\_AON | DI/DO | GPIO\_17 | 7 | uart\_sig\_5\_sel=7 | UART1\_RXD | UART 1 Receive Data | | 16 | 22 | AVDD33\_AON | DI/DO | GPIO\_17 | 7 | uart\_sig\_5\_sel=8 | ISO11898\_TXD | CAN (ISO11898) Transmit Data | | 16 | 22 | AVDD33\_AON | DI/DO | GPIO\_17 | 7 | uart\_sig\_5\_sel=9 | - | - | | 16 | 22 | AVDD33\_AON | DI/DO | GPIO\_17 | 7 | uart\_sig\_5\_sel=10 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 16 | 22 | AVDD33\_AON | DI/DO | GPIO\_17 | 7 | uart\_sig\_5\_sel=11 | ISO11898\_RXD | CAN (ISO 11898) Receive Data | | 16 | 22 | AVDD33\_AON | DI/DO | GPIO\_17 | 8 | - | - | - | | 16 | 22 | AVDD33\_AON | DI/DO | GPIO\_17 | 9 | - | CAM1\_DAT7 | Camera 1 Data 7 (QCC744) | | 16 | 22 | AVDD33\_AON | DI/DO | GPIO\_17 | 10 | - | - | - | | 16 | 22 | AVDD33\_AON | DI/DO | GPIO\_17 | 11 | - | SWGPIO17 | Software GPIO 17 | | 16 | 22 | AVDD33\_AON | DI/DO | GPIO\_17 | 12 | - | - | - | | 16 | 22 | AVDD33\_AON | DI/DO | GPIO\_17 | 16 | reg\_pwm1\_io\_sel=0 | PWM0\_CH1P | PWM 0 Channel 1 Positive | | 16 | 22 | AVDD33\_AON | DI/DO | GPIO\_17 | 16 | reg\_pwm1\_io\_sel=1 | PWM0\_CH0N | PWM 0 Channel 0 Negative | | 16 | 22 | AVDD33\_AON | DI/DO | GPIO\_17 | 22 | - | - | - | | 16 | 22 | AVDD33\_AON | DI/DO | GPIO\_17 | 23 | - | - | - | | 16 | 22 | AVDD33\_AON | DI/DO | GPIO\_17 | 24 | - | - | - | | 16 | 22 | AVDD33\_AON | DI/DO | GPIO\_17 | 25 | - | - | - | | 16 | 22 | AVDD33\_AON | DI/DO | GPIO\_17 | 26 | - | M0\_JTAG\_TCK | M0 JTAG Test Clock | | - | 23 | AVDD33\_AON | DI/DO | GPIO\_18 | 0 | - | - | - | | - | 23 | AVDD33\_AON | DI/DO | GPIO\_18 | 1 | - | SPI\_MISO | SPI Master Input, Slave Output | | - | 23 | AVDD33\_AON | DI/DO | GPIO\_18 | 2 | - | - | | | - | 23 | AVDD33\_AON | DI/DO | GPIO\_18 | 3 | - | I2S\_DI/I2S\_RCLK\_O | I^2^S Data Input/I^2^S Receive Clock Output | | - | 23 | AVDD33\_AON | DI/DO | GPIO\_18 | 4 | - | - | - | | - | 23 | AVDD33\_AON | DI/DO | GPIO\_18 | 5 | - | I2C0\_SCL | I^2^C 0 Serial Clock | | - | 23 | AVDD33\_AON | DI/DO | GPIO\_18 | 6 | - | I2C1\_SCL | I^2^C 1 Serial Clock | | - | 23 | AVDD33\_AON | DI/DO | GPIO\_18 | 7 | uart\_sig\_6\_sel=0 | UART0\_RTS | UART 0 Request To Send | | - | 23 | AVDD33\_AON | DI/DO | GPIO\_18 | 7 | uart\_sig\_6\_sel=1 | UART0\_CTS | UART 0 Clear To Send | | - | 23 | AVDD33\_AON | DI/DO | GPIO\_18 | 7 | uart\_sig\_6\_sel=2 | UART0\_TXD | UART 0 Transmit Data | | - | 23 | AVDD33\_AON | DI/DO | GPIO\_18 | 7 | uart\_sig\_6\_sel=3 | UART0\_RXD | UART 0 Receive Data | | - | 23 | AVDD33\_AON | DI/DO | GPIO\_18 | 7 | uart\_sig\_6\_sel=4 | UART1\_RTS | UART 1 Request To Send | | - | 23 | AVDD33\_AON | DI/DO | GPIO\_18 | 7 | uart\_sig\_6\_sel=5 | UART1\_CTS | UART 1 Clear To Send | | - | 23 | AVDD33\_AON | DI/DO | GPIO\_18 | 7 | uart\_sig\_6\_sel=6 | UART1\_TXD | UART 1 Transmit Data | | - | 23 | AVDD33\_AON | DI/DO | GPIO\_18 | 7 | uart\_sig\_6\_sel=7 | UART1\_RXD | UART 1 Receive Data | | - | 23 | AVDD33\_AON | DI/DO | GPIO\_18 | 7 | uart\_sig\_6\_sel=8 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | - | 23 | AVDD33\_AON | DI/DO | GPIO\_18 | 7 | uart\_sig\_6\_sel=9 | - | - | | - | 23 | AVDD33\_AON | DI/DO | GPIO\_18 | 7 | uart\_sig\_6\_sel=10 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | - | 23 | AVDD33\_AON | DI/DO | GPIO\_18 | 7 | uart\_sig\_6\_sel=11 | ISO11898\_RXD | CAN (ISO 11898) Receive Data | | - | 23 | AVDD33\_AON | DI/DO | GPIO\_18 | 8 | - | - | - | | - | 23 | AVDD33\_AON | DI/DO | GPIO\_18 | 9 | - | - | - | | - | 23 | AVDD33\_AON | DI/DO | GPIO\_18 | 10 | - | - | - | | - | 23 | AVDD33\_AON | DI/DO | GPIO\_18 | 11 | - | SWGPIO18 | Software GPIO 18 | | - | 23 | AVDD33\_AON | DI/DO | GPIO\_18 | 12 | - | - | - | | - | 23 | AVDD33\_AON | DI/DO | GPIO\_18 | 16 | reg\_pwm1\_io\_sel=0 | PWM0\_CH2P | PWM 0 Channel 2 Positive | | - | 23 | AVDD33\_AON | DI/DO | GPIO\_18 | 16 | reg\_pwm1\_io\_sel=1 | PWM0\_CH1P | PWM 0 Channel 1 Positive | | - | 23 | AVDD33\_AON | DI/DO | GPIO\_18 | 22 | - | - | - | | - | 23 | AVDD33\_AON | DI/DO | GPIO\_18 | 23 | - | - | - | | - | 23 | AVDD33\_AON | DI/DO | GPIO\_18 | 24 | - | - | - | | - | 23 | AVDD33\_AON | DI/DO | GPIO\_18 | 25 | - | - | - | | - | 23 | AVDD33\_AON | DI/DO | GPIO\_18 | 26 | - | M0\_JTAG\_TDO | M0 JTAG Test Data Out | | - | 24 | AVDD33\_AON | DI/DO | GPIO\_19 | 0 | - | - | - | | - | 24 | AVDD33\_AON | DI/DO | GPIO\_19 | 1 | - | SPI\_MOSI | SPI Master Output, Slave Input | | - | 24 | AVDD33\_AON | DI/DO | GPIO\_19 | 2 | - | - | - | | - | 24 | AVDD33\_AON | DI/DO | GPIO\_19 | 3 | - | I2S\_DO/I2S\_RCLK\_O | I^2^S Data Output/I^2^S Receive Clock
Output | | - | 24 | AVDD33\_AON | DI/DO | GPIO\_19 | 4 | - | - | - | | - | 24 | AVDD33\_AON | DI/DO | GPIO\_19 | 5 | - | I2C0\_SDA | I^2^C 0 Serial Data | | - | 24 | AVDD33\_AON | DI/DO | GPIO\_19 | 6 | - | I2C1\_SDA | I^2^C 1 Serial Data | | - | 24 | AVDD33\_AON | DI/DO | GPIO\_19 | 7 | uart\_sig\_7\_sel=0 | UART0\_RTS | UART 0 Request To Send | | - | 24 | AVDD33\_AON | DI/DO | GPIO\_19 | 7 | uart\_sig\_7\_sel=1 | UART0\_CTS | UART 0 Clear To Send | | - | 24 | AVDD33\_AON | DI/DO | GPIO\_19 | 7 | uart\_sig\_7\_sel=2 | UART0\_TXD | UART 0 Transmit Data | | - | 24 | AVDD33\_AON | DI/DO | GPIO\_19 | 7 | uart\_sig\_7\_sel=3 | UART0\_RXD | UART 0 Receive Data | | - | 24 | AVDD33\_AON | DI/DO | GPIO\_19 | 7 | uart\_sig\_7\_sel=4 | UART1\_RTS | UART 1 Request To Send | | - | 24 | AVDD33\_AON | DI/DO | GPIO\_19 | 7 | uart\_sig\_7\_sel=5 | UART1\_CTS | UART 1 Clear To Send | | - | 24 | AVDD33\_AON | DI/DO | GPIO\_19 | 7 | uart\_sig\_7\_sel=6 | UART1\_TXD | UART 1 Transmit Data | | - | 24 | AVDD33\_AON | DI/DO | GPIO\_19 | 7 | uart\_sig\_7\_sel=7 | UART1\_RXD | UART 1 Receive Data | | - | 24 | AVDD33\_AON | DI/DO | GPIO\_19 | 7 | uart\_sig\_7\_sel=8 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | - | 24 | AVDD33\_AON | DI/DO | GPIO\_19 | 7 | uart\_sig\_7\_sel=9 | - | - | | - | 24 | AVDD33\_AON | DI/DO | GPIO\_19 | 7 | uart\_sig\_7\_sel=10 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | - | 24 | AVDD33\_AON | DI/DO | GPIO\_19 | 7 | uart\_sig\_7\_sel=11 | ISO11898\_RXD | CAN (ISO 11898) Receive Data | | - | 24 | AVDD33\_AON | DI/DO | GPIO\_19 | 8 | - | - | - | | - | 24 | AVDD33\_AON | DI/DO | GPIO\_19 | 9 | - | - | - | | - | 24 | AVDD33\_AON | DI/DO | GPIO\_19 | 10 | - | ADC\_CH1 | ADC Channel 1 | | - | 24 | AVDD33\_AON | DI/DO | GPIO\_19 | 11 | - | SWGPIO19 | Software GPIO 19 | | - | 24 | AVDD33\_AON | DI/DO | GPIO\_19 | 12 | - | - | - | | - | 24 | AVDD33\_AON | DI/DO | GPIO\_19 | 16 | reg\_pwm1\_io\_sel=0 | PWM0\_CH3P | PWM 0 Channel 3 Positive | | - | 24 | AVDD33\_AON | DI/DO | GPIO\_19 | 16 | reg\_pwm1\_io\_sel=1 | PWM0\_CH1N | PWM 0 Channel 1 Negative | | - | 24 | AVDD33\_AON | DI/DO | GPIO\_19 | 22 | - | - | - | | - | 24 | AVDD33\_AON | DI/DO | GPIO\_19 | 23 | - | - | - | | - | 24 | AVDD33\_AON | DI/DO | GPIO\_19 | 24 | - | - | - | | - | 24 | AVDD33\_AON | DI/DO | GPIO\_19 | 25 | - | - | - | | - | 24 | AVDD33\_AON | DI/DO | GPIO\_19 | 26 | - | M0\_JTAG\_TDI | M0 JTAG Test Data Input | | 17 | 25 | AVDD33\_AON | Analog | CHIP\_EN | | | CHIP\_EN | CHIP\_EN | | 18 | 26 | - | Power, Input | AVDD33\_AON | - | - | AVDD33\_AON | 3.3 V power supply for always-on circuits | | 19 | 27 | - | Power, Output | VDD18\_FLASH | - | - | VDD18\_FLASH | 1.8 V/3.3 V power supply for built-in flash/pSRAM (internal regulator
output) | | 20 | 28 | - | Power, Input | PVDD33\_DCDC | - | - | PVDD33\_DCDC | 3.3 V power supply for DCDC | | 21 | 29 | - | Power, Output | SW\_DCDC | - | - | SW\_DCDC | Switch PIN of DCDC | | 22 | 30 | - | Power,Inout | DCDC\_OUT | - | - | DCDC\_OUT | DCDC output | | 23 | 31 | - | Power, Output | DVDD11 | - | - | DVDD11 | Power supply of digital core (internal regulator output) | | 24 | 32 | | Power, Input | VDD33 | - | - | VDD33 | 3.3 V power supply of audadc | | 25, 26 | 33, 34 | | - | NC | | | - | Not connected | | 27 | 35 | VDDIO\_2 | DI/DO | GPIO\_20 | 0 | - | - | - | | 27 | 35 | VDDIO\_2 | DI/DO | GPIO\_20 | 1 | - | SPI\_SS | SPI Slave Select | | 27 | 35 | VDDIO\_2 | DI/DO | GPIO\_20 | 2 | - | - | - | | 27 | 35 | VDDIO\_2 | DI/DO | GPIO\_20 | 3 | - | I2S\_BCLK | I^2^S Bit Clock | | 27 | 35 | VDDIO\_2 | DI/DO | GPIO\_20 | 4 | - | PDM\_CLK\_O | PDM Clock Line | | 27 | 35 | VDDIO\_2 | DI/DO | GPIO\_20 | 5 | - | I2C0\_SCL | I^2^C 0 Serial Clock | | 27 | 35 | VDDIO\_2 | DI/DO | GPIO\_20 | 6 | - | I2C1\_SCL | I^2^C 1 Serial Clock | | 27 | 35 | VDDIO\_2 | DI/DO | GPIO\_20 | 7 | uart\_sig\_8\_sel=0 | UART0\_RTS | UART 0 Request To Send | | 27 | 35 | VDDIO\_2 | DI/DO | GPIO\_20 | 7 | uart\_sig\_8\_sel=1 | UART0\_CTS | UART 0 Clear To Send | | 27 | 35 | VDDIO\_2 | DI/DO | GPIO\_20 | 7 | uart\_sig\_8\_sel=2 | UART0\_TXD | UART 0 Transmit Data | | 27 | 35 | VDDIO\_2 | DI/DO | GPIO\_20 | 7 | uart\_sig\_8\_sel=3 | UART0\_RXD | UART 0 Receive Data | | 27 | 35 | VDDIO\_2 | DI/DO | GPIO\_20 | 7 | uart\_sig\_8\_sel=4 | UART1\_RTS | UART 1 Request To Send | | 27 | 35 | VDDIO\_2 | DI/DO | GPIO\_20 | 7 | uart\_sig\_8\_sel=5 | UART1\_CTS | UART 1 Clear To Send | | 27 | 35 | VDDIO\_2 | DI/DO | GPIO\_20 | 7 | uart\_sig\_8\_sel=6 | UART1\_TXD | UART 1 Transmit Data | | 27 | 35 | VDDIO\_2 | DI/DO | GPIO\_20 | 7 | uart\_sig\_8\_sel=7 | UART1\_RXD | UART 1 Receive Data | | 27 | 35 | VDDIO\_2 | DI/DO | GPIO\_20 | 7 | uart\_sig\_8\_sel=8 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 27 | 35 | VDDIO\_2 | DI/DO | GPIO\_20 | 7 | uart\_sig\_8\_sel=9 | - | - | | 27 | 35 | VDDIO\_2 | DI/DO | GPIO\_20 | 7 | uart\_sig\_8\_sel=10 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 27 | 35 | VDDIO\_2 | DI/DO | GPIO\_20 | 7 | uart\_sig\_8\_sel=11 | ISO11898\_RXD | CAN (ISO 11898) Receive Data | | 27 | 35 | VDDIO\_2 | DI/DO | GPIO\_20 | 8 | - | - | - | | 27 | 35 | VDDIO\_2 | DI/DO | GPIO\_20 | 9 | - | - | - | | 27 | 35 | VDDIO\_2 | DI/DO | GPIO\_20 | 10 | - | ADC\_CH0/AUADC\_CH0 | ADC Channel 0/ Audio ADC Channel 0



(QCC744) | | 27 | 35 | VDDIO\_2 | DI/DO | GPIO\_20 | 11 | - | SWGPIO20 | Software GPIO 20 | | 27 | 35 | VDDIO\_2 | DI/DO | GPIO\_20 | 12 | - | - | - | | 27 | 35 | VDDIO\_2 | DI/DO | GPIO\_20 | 16 | reg\_pwm1\_io\_sel=0 | PWM0\_CH0P | PWM 0 Channel 0 Positive | | 27 | 35 | VDDIO\_2 | DI/DO | GPIO\_20 | 16 | reg\_pwm1\_io\_sel=1 | PWM0\_CH2P | PWM 0 Channel 2 Positive | | 27 | 35 | VDDIO\_2 | DI/DO | GPIO\_20 | 22 | - | - | - | | 27 | 35 | VDDIO\_2 | DI/DO | GPIO\_20 | 23 | - | - | - | | 27 | 35 | VDDIO\_2 | DI/DO | GPIO\_20 | 24 | - | - | - | | 27 | 35 | VDDIO\_2 | DI/DO | GPIO\_20 | 25 | - | - | - | | 27 | 35 | VDDIO\_2 | DI/DO | GPIO\_20 | 26 | - | M0\_JTAG\_TMS | M0 JTAG Test Mode Select | | 28 | 36 | VDDIO\_2 | DI/DO | GPIO\_21 | 0 | - | - | - | | 28 | 36 | VDDIO\_2 | DI/DO | GPIO\_21 | 1 | - | SPI\_SCLK | SPI Serial Clock | | 28 | 36 | VDDIO\_2 | DI/DO | GPIO\_21 | 2 | - | - | - | | 28 | 36 | VDDIO\_2 | DI/DO | GPIO\_21 | 3 | - | I2S\_FS | I^2^S Frame Sync | | 28 | 36 | VDDIO\_2 | DI/DO | GPIO\_21 | 4 | - | PDM\_0\_IN | PDM Data Line | | 28 | 36 | VDDIO\_2 | DI/DO | GPIO\_21 | 5 | - | I2C0\_SDA | I^2^C 0 Serial Data | | 28 | 36 | VDDIO\_2 | DI/DO | GPIO\_21 | 6 | - | I2C1\_SDA | I^2^C 1 Serial Data | | 28 | 36 | VDDIO\_2 | DI/DO | GPIO\_21 | 7 | uart\_sig\_9\_sel=0 | UART0\_RTS | UART 0 Request To Send | | 28 | 36 | VDDIO\_2 | DI/DO | GPIO\_21 | 7 | uart\_sig\_9\_sel=1 | UART0\_CTS | UART 0 Clear To Send | | 28 | 36 | VDDIO\_2 | DI/DO | GPIO\_21 | 7 | uart\_sig\_9\_sel=2 | UART0\_TXD | UART 0 Transmit Data | | 28 | 36 | VDDIO\_2 | DI/DO | GPIO\_21 | 7 | uart\_sig\_9\_sel=3 | UART0\_RXD | UART 0 Receive Data | | 28 | 36 | VDDIO\_2 | DI/DO | GPIO\_21 | 7 | uart\_sig\_9\_sel=4 | UART1\_RTS | UART 1 Request To Send | | 28 | 36 | VDDIO\_2 | DI/DO | GPIO\_21 | 7 | uart\_sig\_9\_sel=5 | UART1\_CTS | UART 1 Clear To Send | | 28 | 36 | VDDIO\_2 | DI/DO | GPIO\_21 | 7 | uart\_sig\_9\_sel=6 | UART1\_TXD | UART 1 Transmit Data | | 28 | 36 | VDDIO\_2 | DI/DO | GPIO\_21 | 7 | uart\_sig\_9\_sel=7 | UART1\_RXD | UART 1 Receive Data | | 28 | 36 | VDDIO\_2 | DI/DO | GPIO\_21 | 7 | uart\_sig\_9\_sel=8 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 28 | 36 | VDDIO\_2 | DI/DO | GPIO\_21 | 7 | uart\_sig\_9\_sel=9 | - | - | | 28 | 36 | VDDIO\_2 | DI/DO | GPIO\_21 | 7 | uart\_sig\_9\_sel=10 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 28 | 36 | VDDIO\_2 | DI/DO | GPIO\_21 | 7 | uart\_sig\_9\_sel=11 | ISO11898\_RXD | CAN (ISO 11898) Receive Data | | 28 | 36 | VDDIO\_2 | DI/DO | GPIO\_21 | 8 | - | - | - | | 28 | 36 | VDDIO\_2 | DI/DO | GPIO\_21 | 9 | - | - | - | | 28 | 36 | VDDIO\_2 | DI/DO | GPIO\_21 | 10 | - | - | - | | 28 | 36 | VDDIO\_2 | DI/DO | GPIO\_21 | 11 | - | SWGPIO21 | Software GPIO 21 | | 28 | 36 | VDDIO\_2 | DI/DO | GPIO\_21 | 12 | - | - | - | | 28 | 36 | VDDIO\_2 | DI/DO | GPIO\_21 | 16 | reg\_pwm1\_io\_sel=0 | PWM0\_CH1P | PWM 0 Channel 1 Positive | | 28 | 36 | VDDIO\_2 | DI/DO | GPIO\_21 | 16 | reg\_pwm1\_io\_sel=1 | PWM0\_CH2N | PWM 0 Channel 2 Negative | | 28 | 36 | VDDIO\_2 | DI/DO | GPIO\_21 | 22 | - | - | - | | 28 | 36 | VDDIO\_2 | DI/DO | GPIO\_21 | 23 | - | - | - | | 28 | 36 | VDDIO\_2 | DI/DO | GPIO\_21 | 24 | - | - | - | | 28 | 36 | VDDIO\_2 | DI/DO | GPIO\_21 | 25 | - | - | - | | 28 | 36 | VDDIO\_2 | DI/DO | GPIO\_21 | 26 | - | M0\_JTAG\_TCK | M0 JTAG Test Clock | | 29 | 37 | VDDIO\_2 | DI/DO | GPIO\_22 | 0 | - | - | - | | 29 | 37 | VDDIO\_2 | DI/DO | GPIO\_22 | 1 | - | SPI\_MISO | SPI Master Input, Slave Output | | 29 | 37 | VDDIO\_2 | DI/DO | GPIO\_22 | 2 | - | - | | | 29 | 37 | VDDIO\_2 | DI/DO | GPIO\_22 | 3 | - | I2S\_DI/I2S\_RCLK\_O | I^2^S Data Input/I^2^S Receive Clock Output | | 29 | 37 | VDDIO\_2 | DI/DO | GPIO\_22 | 4 | - | - | - | | 29 | 37 | VDDIO\_2 | DI/DO | GPIO\_22 | 5 | - | I2C0\_SCL | I^2^C 0 Serial Clock | | 29 | 37 | VDDIO\_2 | DI/DO | GPIO\_22 | 6 | - | I2C1\_SCL | I^2^C 1 Serial Clock | | 29 | 37 | VDDIO\_2 | DI/DO | GPIO\_22 | 7 | uart\_sig\_10\_sel=0 | UART0\_RTS | UART 0 Request To Send | | 29 | 37 | VDDIO\_2 | DI/DO | GPIO\_22 | 7 | uart\_sig\_10\_sel=1 | UART0\_CTS | UART 0 Clear To Send | | 29 | 37 | VDDIO\_2 | DI/DO | GPIO\_22 | 7 | uart\_sig\_10\_sel=2 | UART0\_TXD | UART 0 Transmit Data | | 29 | 37 | VDDIO\_2 | DI/DO | GPIO\_22 | 7 | uart\_sig\_10\_sel=3 | UART0\_RXD | UART 0 Receive Data | | 29 | 37 | VDDIO\_2 | DI/DO | GPIO\_22 | 7 | uart\_sig\_10\_sel=4 | UART1\_RTS | UART 1 Request To Send | | 29 | 37 | VDDIO\_2 | DI/DO | GPIO\_22 | 7 | uart\_sig\_10\_sel=5 | UART1\_CTS | UART 1 Clear To Send | | 29 | 37 | VDDIO\_2 | DI/DO | GPIO\_22 | 7 | uart\_sig\_10\_sel=6 | UART1\_TXD | UART 1 Transmit Data | | 29 | 37 | VDDIO\_2 | DI/DO | GPIO\_22 | 7 | uart\_sig\_10\_sel=7 | UART1\_RXD | UART 1 Receive Data | | 29 | 37 | VDDIO\_2 | DI/DO | GPIO\_22 | 7 | uart\_sig\_10\_sel=8 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 29 | 37 | VDDIO\_2 | DI/DO | GPIO\_22 | 7 | uart\_sig\_10\_sel=9 | - | - | | 29 | 37 | VDDIO\_2 | DI/DO | GPIO\_22 | 7 | uart\_sig\_10\_sel=10 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 29 | 37 | VDDIO\_2 | DI/DO | GPIO\_22 | 7 | uart\_sig\_10\_sel=11 | ISO11898\_RXD | CAN (ISO 11898) Receive Data | | 29 | 37 | VDDIO\_2 | DI/DO | GPIO\_22 | 8 | - | - | - | | 29 | 37 | VDDIO\_2 | DI/DO | GPIO\_22 | 9 | - | - | - | | 29 | 37 | VDDIO\_2 | DI/DO | GPIO\_22 | 10 | - | - | - | | 29 | 37 | VDDIO\_2 | DI/DO | GPIO\_22 | 11 | - | SWGPIO22 | Software GPIO 22 | | 29 | 37 | VDDIO\_2 | DI/DO | GPIO\_22 | 12 | - | - | - | | 29 | 37 | VDDIO\_2 | DI/DO | GPIO\_22 | 16 | reg\_pwm1\_io\_sel=0 | PWM0\_CH2P | PWM 0 Channel 2 Positive | | 29 | 37 | VDDIO\_2 | DI/DO | GPIO\_22 | 16 | reg\_pwm1\_io\_sel=1 | PWM0\_CH3P | PWM 0 Channel 3 Positive | | 29 | 37 | VDDIO\_2 | DI/DO | GPIO\_22 | 22 | - | - | - | | 29 | 37 | VDDIO\_2 | DI/DO | GPIO\_22 | 23 | - | - | - | | 29 | 37 | VDDIO\_2 | DI/DO | GPIO\_22 | 24 | - | - | - | | 29 | 37 | VDDIO\_2 | DI/DO | GPIO\_22 | 25 | - | AUDAC\_PWM\_P | AUDAC\_PWM\_P | | 29 | 37 | VDDIO\_2 | DI/DO | GPIO\_22 | 26 | - | M0\_JTAG\_TDO | M0 JTAG Test Data Out | | - | 38 | VDDIO\_2 | DI/DO | GPIO\_23 | 0 | - | - | - | | - | 38 | VDDIO\_2 | DI/DO | GPIO\_23 | 1 | - | SPI\_MOSI | SPI Master Output, Slave Input | | - | 38 | VDDIO\_2 | DI/DO | GPIO\_23 | 2 | - | - | - | | - | 38 | VDDIO\_2 | DI/DO | GPIO\_23 | 3 | - | I2S\_DO/I2S\_RCLK\_O | I^2^S Data Output/I^2^S Receive Clock
Output | | - | 38 | VDDIO\_2 | DI/DO | GPIO\_23 | 4 | - | - | - | | - | 38 | VDDIO\_2 | DI/DO | GPIO\_23 | 5 | - | I2C0\_SDA | I^2^C 0 Serial Data | | - | 38 | VDDIO\_2 | DI/DO | GPIO\_23 | 6 | - | I2C1\_SDA | I^2^C 1 Serial Data | | - | 38 | VDDIO\_2 | DI/DO | GPIO\_23 | 7 | uart\_sig\_11\_sel=0 | UART0\_RTS | UART 0 Request To Send | | - | 38 | VDDIO\_2 | DI/DO | GPIO\_23 | 7 | uart\_sig\_11\_sel=1 | UART0\_CTS | UART 0 Clear To Send | | - | 38 | VDDIO\_2 | DI/DO | GPIO\_23 | 7 | uart\_sig\_11\_sel=2 | UART0\_TXD | UART 0 Transmit Data | | - | 38 | VDDIO\_2 | DI/DO | GPIO\_23 | 7 | uart\_sig\_11\_sel=3 | UART0\_RXD | UART 0 Receive Data | | - | 38 | VDDIO\_2 | DI/DO | GPIO\_23 | 7 | uart\_sig\_11\_sel=4 | UART1\_RTS | UART 1 Request To Send | | - | 38 | VDDIO\_2 | DI/DO | GPIO\_23 | 7 | uart\_sig\_11\_sel=5 | UART1\_CTS | UART 1 Clear To Send | | - | 38 | VDDIO\_2 | DI/DO | GPIO\_23 | 7 | uart\_sig\_11\_sel=6 | UART1\_TXD | UART 1 Transmit Data | | - | 38 | VDDIO\_2 | DI/DO | GPIO\_23 | 7 | uart\_sig\_11\_sel=7 | UART1\_RXD | UART 1 Receive Data | | - | 38 | VDDIO\_2 | DI/DO | GPIO\_23 | 7 | uart\_sig\_11\_sel=8 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | - | 38 | VDDIO\_2 | DI/DO | GPIO\_23 | 7 | uart\_sig\_11\_sel=9 | - | - | | - | 38 | VDDIO\_2 | DI/DO | GPIO\_23 | 7 | uart\_sig\_11\_sel=10 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | - | 38 | VDDIO\_2 | DI/DO | GPIO\_23 | 7 | uart\_sig\_11\_sel=11 | ISO11898\_RXD | CAN (ISO 11898) Receive Data | | - | 38 | VDDIO\_2 | DI/DO | GPIO\_23 | 8 | - | - | - | | - | 38 | VDDIO\_2 | DI/DO | GPIO\_23 | 9 | - | - | - | | - | 38 | VDDIO\_2 | DI/DO | GPIO\_23 | 10 | - | AUADC\_CH3 | Audio ADC Channel 3 (QCC744) | | - | 38 | VDDIO\_2 | DI/DO | GPIO\_23 | 11 | - | SWGPIO23 | Software GPIO 23 | | - | 38 | VDDIO\_2 | DI/DO | GPIO\_23 | 12 | - | - | - | | - | 38 | VDDIO\_2 | DI/DO | GPIO\_23 | 16 | reg\_pwm1\_io\_sel=0 | PWM0\_CH3P | PWM 0 Channel 3 Positive | | - | 38 | VDDIO\_2 | DI/DO | GPIO\_23 | 16 | reg\_pwm1\_io\_sel=1 | PWM0\_CH3N | PWM 0 Channel 3 Negative | | - | 38 | VDDIO\_2 | DI/DO | GPIO\_23 | 22 | - | - | - | | - | 38 | VDDIO\_2 | DI/DO | GPIO\_23 | 23 | - | - | - | | - | 38 | VDDIO\_2 | DI/DO | GPIO\_23 | 24 | - | - | - | | - | 38 | VDDIO\_2 | DI/DO | GPIO\_23 | 25 | - | AUDAC\_PWM\_N | AUDAC\_PWM\_N | | - | 38 | VDDIO\_2 | DI/DO | GPIO\_23 | 26 | - | M0\_JTAG\_TDI | M0 JTAG Test Data Input | | - | 39 | VDDIO\_2 | DI/DO | GPIO\_24 | 0 | - | - | - | | - | 39 | VDDIO\_2 | DI/DO | GPIO\_24 | 1 | - | SPI\_SS | SPI Slave Select | | - | 39 | VDDIO\_2 | DI/DO | GPIO\_24 | 2 | - | - | - | | - | 39 | VDDIO\_2 | DI/DO | GPIO\_24 | 3 | - | I2S\_BCLK | I^2^S Bit Clock | | - | 39 | VDDIO\_2 | DI/DO | GPIO\_24 | 4 | - | - | - | | - | 39 | VDDIO\_2 | DI/DO | GPIO\_24 | 5 | - | I2C0\_SCL | I^2^C 0 Serial Clock | | - | 39 | VDDIO\_2 | DI/DO | GPIO\_24 | 6 | - | I2C1\_SCL | I^2^C 1 Serial Clock | | - | 39 | VDDIO\_2 | DI/DO | GPIO\_24 | 7 | uart\_sig\_0\_sel=0 | UART0\_RTS | UART 0 Request To Send | | - | 39 | VDDIO\_2 | DI/DO | GPIO\_24 | 7 | uart\_sig\_0\_sel=1 | UART0\_CTS | UART 0 Clear To Send | | - | 39 | VDDIO\_2 | DI/DO | GPIO\_24 | 7 | uart\_sig\_0\_sel=2 | UART0\_TXD | UART 0 Transmit Data | | - | 39 | VDDIO\_2 | DI/DO | GPIO\_24 | 7 | uart\_sig\_0\_sel=3 | UART0\_RXD | UART 0 Receive Data | | - | 39 | VDDIO\_2 | DI/DO | GPIO\_24 | 7 | uart\_sig\_0\_sel=4 | UART1\_RTS | UART 1 Request To Send | | - | 39 | VDDIO\_2 | DI/DO | GPIO\_24 | 7 | uart\_sig\_0\_sel=5 | UART1\_CTS | UART 1 Clear To Send | | - | 39 | VDDIO\_2 | DI/DO | GPIO\_24 | 7 | uart\_sig\_0\_sel=6 | UART1\_TXD | UART 1 Transmit Data | | - | 39 | VDDIO\_2 | DI/DO | GPIO\_24 | 7 | uart\_sig\_0\_sel=7 | UART1\_RXD | UART 1 Receive Data | | - | 39 | VDDIO\_2 | DI/DO | GPIO\_24 | 7 | uart\_sig\_0\_sel=8 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | - | 39 | VDDIO\_2 | DI/DO | GPIO\_24 | 7 | uart\_sig\_0\_sel=9 | - | - | | - | 39 | VDDIO\_2 | DI/DO | GPIO\_24 | 7 | uart\_sig\_0\_sel=10 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | - | 39 | VDDIO\_2 | DI/DO | GPIO\_24 | 7 | uart\_sig\_0\_sel=11 | ISO11898\_RXD | CAN (ISO 11898) Receive Data | | - | 39 | VDDIO\_2 | DI/DO | GPIO\_24 | 8 | - | - | - | | - | 39 | VDDIO\_2 | DI/DO | GPIO\_24 | 9 | - | CAM0\_DAT0 | Camera 0 Data 0 (QCC744) | | - | 39 | VDDIO\_2 | DI/DO | GPIO\_24 | 10 | - | - | - | | - | 39 | VDDIO\_2 | DI/DO | GPIO\_24 | 11 | - | SWGPIO24 | Software GPIO 24 | | - | 39 | VDDIO\_2 | DI/DO | GPIO\_24 | 12 | - | - | - | | - | 39 | VDDIO\_2 | DI/DO | GPIO\_24 | 16 | reg\_pwm1\_io\_sel=0 | PWM0\_CH0P | PWM 0 Channel 0 Positive | | - | 39 | VDDIO\_2 | DI/DO | GPIO\_24 | 16 | reg\_pwm1\_io\_sel=1 | PWM0\_CH0P | PWM 0 Channel 0 Positive | | - | 39 | VDDIO\_2 | DI/DO | GPIO\_24 | 22 | - | - | - | | - | 39 | VDDIO\_2 | DI/DO | GPIO\_24 | 23 | - | - | - | | - | 39 | VDDIO\_2 | DI/DO | GPIO\_24 | 24 | - | - | - | | - | 39 | VDDIO\_2 | DI/DO | GPIO\_24 | 25 | - | - | - | | - | 39 | VDDIO\_2 | DI/DO | GPIO\_24 | 26 | - | M0\_JTAG\_TMS | M0 JTAG Test Mode Select | | - | 40 | VDDIO\_2 | DI/DO | GPIO\_25 | 0 | - | - | - | | - | 40 | VDDIO\_2 | DI/DO | GPIO\_25 | 1 | - | SPI\_SCLK | SPI Serial Clock | | - | 40 | VDDIO\_2 | DI/DO | GPIO\_25 | 2 | - | - | - | | - | 40 | VDDIO\_2 | DI/DO | GPIO\_25 | 3 | - | I2S\_FS | I^2^S Frame Sync | | - | 40 | VDDIO\_2 | DI/DO | GPIO\_25 | 4 | - | PDM\_0\_IN | PDM Data Line | | - | 40 | VDDIO\_2 | DI/DO | GPIO\_25 | 5 | - | I2C0\_SDA | I^2^C 0 Serial Data | | - | 40 | VDDIO\_2 | DI/DO | GPIO\_25 | 6 | - | I2C1\_SDA | I^2^C 1 Serial Data | | - | 40 | VDDIO\_2 | DI/DO | GPIO\_25 | 7 | uart\_sig\_1\_sel=0 | UART0\_RTS | UART 0 Request To Send | | - | 40 | VDDIO\_2 | DI/DO | GPIO\_25 | 7 | uart\_sig\_1\_sel=1 | UART0\_CTS | UART 0 Clear To Send | | - | 40 | VDDIO\_2 | DI/DO | GPIO\_25 | 7 | uart\_sig\_1\_sel=2 | UART0\_TXD | UART 0 Transmit Data | | - | 40 | VDDIO\_2 | DI/DO | GPIO\_25 | 7 | uart\_sig\_1\_sel=3 | UART0\_RXD | UART 0 Receive Data | | - | 40 | VDDIO\_2 | DI/DO | GPIO\_25 | 7 | uart\_sig\_1\_sel=4 | UART1\_RTS | UART 1 Request To Send | | - | 40 | VDDIO\_2 | DI/DO | GPIO\_25 | 7 | uart\_sig\_1\_sel=5 | UART1\_CTS | UART 1 Clear To Send | | - | 40 | VDDIO\_2 | DI/DO | GPIO\_25 | 7 | uart\_sig\_1\_sel=6 | UART1\_TXD | UART 1 Transmit Data | | - | 40 | VDDIO\_2 | DI/DO | GPIO\_25 | 7 | uart\_sig\_1\_sel=7 | UART1\_RXD | UART 1 Receive Data | | - | 40 | VDDIO\_2 | DI/DO | GPIO\_25 | 7 | uart\_sig\_1\_sel=8 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | - | 40 | VDDIO\_2 | DI/DO | GPIO\_25 | 7 | uart\_sig\_1\_sel=9 | - | - | | - | 40 | VDDIO\_2 | DI/DO | GPIO\_25 | 7 | uart\_sig\_1\_sel=10 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | - | 40 | VDDIO\_2 | DI/DO | GPIO\_25 | 7 | uart\_sig\_1\_sel=11 | ISO11898\_RXD | CAN (ISO 11898) Receive Data | | - | 40 | VDDIO\_2 | DI/DO | GPIO\_25 | 8 | - | RMII\_REF\_CLK | RMII Reference Clock (QCC744) | | - | 40 | VDDIO\_2 | DI/DO | GPIO\_25 | 9 | - | CAM0\_DAT1 | Camera 0 Data 1 (QCC744) | | - | 40 | VDDIO\_2 | DI/DO | GPIO\_25 | 10 | - | - | - | | - | 40 | VDDIO\_2 | DI/DO | GPIO\_25 | 11 | - | SWGPIO25 | Software GPIO 25 | | - | 40 | VDDIO\_2 | DI/DO | GPIO\_25 | 12 | - | - | - | | - | 40 | VDDIO\_2 | DI/DO | GPIO\_25 | 16 | reg\_pwm1\_io\_sel=0 | PWM0\_CH1P | PWM 0 Channel 1 Positive | | - | 40 | VDDIO\_2 | DI/DO | GPIO\_25 | 16 | reg\_pwm1\_io\_sel=1 | PWM0\_CH0N | PWM 0 Channel 0 Negative | | - | 40 | VDDIO\_2 | DI/DO | GPIO\_25 | 22 | - | - | - | | - | 40 | VDDIO\_2 | DI/DO | GPIO\_25 | 23 | - | - | - | | - | 40 | VDDIO\_2 | DI/DO | GPIO\_25 | 24 | - | - | - | | - | 40 | VDDIO\_2 | DI/DO | GPIO\_25 | 25 | - | - | - | | - | 40 | VDDIO\_2 | DI/DO | GPIO\_25 | 26 | - | M0\_JTAG\_TCK | M0 JTAG Test Clock | | - | 41 | VDDIO\_2 | DI/DO | GPIO\_26 | 0 | - | - | - | | - | 41 | VDDIO\_2 | DI/DO | GPIO\_26 | 1 | - | SPI\_MISO | SPI Master Input, Slave Output | | - | 41 | VDDIO\_2 | DI/DO | GPIO\_26 | 2 | - | - | | | - | 41 | VDDIO\_2 | DI/DO | GPIO\_26 | 3 | - | I2S\_DI/I2S\_RCLK\_O | I^2^S Data Input/I^2^S Receive Clock Output | | - | 41 | VDDIO\_2 | DI/DO | GPIO\_26 | 4 | - | PDM\_CLK\_O | PDM Clock Line | | - | 41 | VDDIO\_2 | DI/DO | GPIO\_26 | 5 | - | I2C0\_SCL | I^2^C 0 Serial Clock | | - | 41 | VDDIO\_2 | DI/DO | GPIO\_26 | 6 | - | I2C1\_SCL | I^2^C 1 Serial Clock | | - | 41 | VDDIO\_2 | DI/DO | GPIO\_26 | 7 | uart\_sig\_2\_sel=0 | UART0\_RTS | UART 0 Request To Send | | - | 41 | VDDIO\_2 | DI/DO | GPIO\_26 | 7 | uart\_sig\_2\_sel=1 | UART0\_CTS | UART 0 Clear To Send | | - | 41 | VDDIO\_2 | DI/DO | GPIO\_26 | 7 | uart\_sig\_2\_sel=2 | UART0\_TXD | UART 0 Transmit Data | | - | 41 | VDDIO\_2 | DI/DO | GPIO\_26 | 7 | uart\_sig\_2\_sel=3 | UART0\_RXD | UART 0 Receive Data | | - | 41 | VDDIO\_2 | DI/DO | GPIO\_26 | 7 | uart\_sig\_2\_sel=4 | UART1\_RTS | UART 1 Request To Send | | - | 41 | VDDIO\_2 | DI/DO | GPIO\_26 | 7 | uart\_sig\_2\_sel=5 | UART1\_CTS | UART 1 Clear To Send | | - | 41 | VDDIO\_2 | DI/DO | GPIO\_26 | 7 | uart\_sig\_2\_sel=6 | UART1\_TXD | UART 1 Transmit Data | | - | 41 | VDDIO\_2 | DI/DO | GPIO\_26 | 7 | uart\_sig\_2\_sel=7 | UART1\_RXD | UART 1 Receive Data | | - | 41 | VDDIO\_2 | DI/DO | GPIO\_26 | 7 | uart\_sig\_2\_sel=8 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | - | 41 | VDDIO\_2 | DI/DO | GPIO\_26 | 7 | uart\_sig\_2\_sel=9 | - | - | | - | 41 | VDDIO\_2 | DI/DO | GPIO\_26 | 7 | uart\_sig\_2\_sel=10 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | - | 41 | VDDIO\_2 | DI/DO | GPIO\_26 | 7 | uart\_sig\_2\_sel=11 | ISO11898\_RXD | CAN (ISO 11898) Receive Data | | - | 41 | VDDIO\_2 | DI/DO | GPIO\_26 | 8 | - | RMII\_TXD[0] | RMII Transmit Data [0] (QCC744) | | - | 41 | VDDIO\_2 | DI/DO | GPIO\_26 | 9 | - | CAM0\_DAT2 | Camera 0 Data 2 (QCC744) | | - | 41 | VDDIO\_2 | DI/DO | GPIO\_26 | 10 | - | - | - | | - | 41 | VDDIO\_2 | DI/DO | GPIO\_26 | 11 | - | SWGPIO26 | Software GPIO 26 | | - | 41 | VDDIO\_2 | DI/DO | GPIO\_26 | 12 | - | - | - | | - | 41 | VDDIO\_2 | DI/DO | GPIO\_26 | 16 | reg\_pwm1\_io\_sel=0 | PWM0\_CH2P | PWM 0 Channel 2 Positive | | - | 41 | VDDIO\_2 | DI/DO | GPIO\_26 | 16 | reg\_pwm1\_io\_sel=1 | PWM0\_CH1P | PWM 0 Channel 1 Positive | | - | 41 | VDDIO\_2 | DI/DO | GPIO\_26 | 22 | - | - | - | | - | 41 | VDDIO\_2 | DI/DO | GPIO\_26 | 23 | - | - | - | | - | 41 | VDDIO\_2 | DI/DO | GPIO\_26 | 24 | - | - | - | | - | 41 | VDDIO\_2 | DI/DO | GPIO\_26 | 25 | - | - | - | | - | 41 | VDDIO\_2 | DI/DO | GPIO\_26 | 26 | - | M0\_JTAG\_TDO | M0 JTAG Test Data Out | | 30 | 42 | - | Power, Input | VDDIO2 | - | - | VDDIO2 | 1.8 V/3.3 V power supply of GPIO20 -GPIO34 | | 31 | 43 | VDDIO\_2 | DI/DO | GPIO\_27 | 0 | - | - | - | | 31 | 43 | VDDIO\_2 | DI/DO | GPIO\_27 | 1 | - | SPI\_MOSI | SPI Master Output, Slave Input | | 31 | 43 | VDDIO\_2 | DI/DO | GPIO\_27 | 2 | - | - | - | | 31 | 43 | VDDIO\_2 | DI/DO | GPIO\_27 | 3 | - | I2S\_DO/I2S\_RCLK\_O | I^2^S Data Output/I^2^S Receive Clock
Output | | 31 | 43 | VDDIO\_2 | DI/DO | GPIO\_27 | 4 | - | - | - | | 31 | 43 | VDDIO\_2 | DI/DO | GPIO\_27 | 5 | - | I2C0\_SDA | I^2^C 0 Serial Data | | 31 | 43 | VDDIO\_2 | DI/DO | GPIO\_27 | 6 | - | I2C1\_SDA | I^2^C 1 Serial Data | | 31 | 43 | VDDIO\_2 | DI/DO | GPIO\_27 | 7 | uart\_sig\_3\_sel=0 | UART0\_RTS | UART 0 Request To Send | | 31 | 43 | VDDIO\_2 | DI/DO | GPIO\_27 | 7 | uart\_sig\_3\_sel=1 | UART0\_CTS | UART 0 Clear To Send | | 31 | 43 | VDDIO\_2 | DI/DO | GPIO\_27 | 7 | uart\_sig\_3\_sel=2 | UART0\_TXD | UART 0 Transmit Data | | 31 | 43 | VDDIO\_2 | DI/DO | GPIO\_27 | 7 | uart\_sig\_3\_sel=3 | UART0\_RXD | UART 0 Receive Data | | 31 | 43 | VDDIO\_2 | DI/DO | GPIO\_27 | 7 | uart\_sig\_3\_sel=4 | UART1\_RTS | UART 1 Request To Send | | 31 | 43 | VDDIO\_2 | DI/DO | GPIO\_27 | 7 | uart\_sig\_3\_sel=5 | UART1\_CTS | UART 1 Clear To Send | | 31 | 43 | VDDIO\_2 | DI/DO | GPIO\_27 | 7 | uart\_sig\_3\_sel=6 | UART1\_TXD | UART 1 Transmit Data | | 31 | 43 | VDDIO\_2 | DI/DO | GPIO\_27 | 7 | uart\_sig\_3\_sel=7 | UART1\_RXD | UART 1 Receive Data | | 31 | 43 | VDDIO\_2 | DI/DO | GPIO\_27 | 7 | uart\_sig\_3\_sel=8 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 31 | 43 | VDDIO\_2 | DI/DO | GPIO\_27 | 7 | uart\_sig\_3\_sel=9 | - | - | | 31 | 43 | VDDIO\_2 | DI/DO | GPIO\_27 | 7 | uart\_sig\_3\_sel=10 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 31 | 43 | VDDIO\_2 | DI/DO | GPIO\_27 | 7 | uart\_sig\_3\_sel=11 | ISO11898\_RXD | CAN (ISO 11898) Receive Data | | 31 | 43 | VDDIO\_2 | DI/DO | GPIO\_27 | 8 | - | RMII\_TXD[1] | RMII Transmit Data [1] (QCC744) | | 31 | 43 | VDDIO\_2 | DI/DO | GPIO\_27 | 9 | - | CAM0\_DAT3 | Camera 0 Data 3 (QCC744) | | 31 | 43 | VDDIO\_2 | DI/DO | GPIO\_27 | 10 | - | ADC\_CH10/AUADC\_CH4 | ADC Channel 10/Audio ADC Channel 4



(QCC744) | | 31 | 43 | VDDIO\_2 | DI/DO | GPIO\_27 | 11 | - | SWGPIO27 | Software GPIO 27 | | 31 | 43 | VDDIO\_2 | DI/DO | GPIO\_27 | 12 | - | - | - | | 31 | 43 | VDDIO\_2 | DI/DO | GPIO\_27 | 16 | reg\_pwm1\_io\_sel=0 | PWM0\_CH3P | PWM 0 Channel 3 Positive | | 31 | 43 | VDDIO\_2 | DI/DO | GPIO\_27 | 16 | reg\_pwm1\_io\_sel=1 | PWM0\_CH1N | PWM 0 Channel 1 Negative | | 31 | 43 | VDDIO\_2 | DI/DO | GPIO\_27 | 22 | - | - | - | | 31 | 43 | VDDIO\_2 | DI/DO | GPIO\_27 | 23 | - | - | - | | 31 | 43 | VDDIO\_2 | DI/DO | GPIO\_27 | 24 | - | - | - | | 31 | 43 | VDDIO\_2 | DI/DO | GPIO\_27 | 25 | - | AUDAC\_PWM\_N | AUDAC\_PWM\_N | | 31 | 43 | VDDIO\_2 | DI/DO | GPIO\_27 | 26 | - | M0\_JTAG\_TDI | M0 JTAG Test Data Input | | 32 | 44 | VDDIO\_2 | DI/DO | GPIO\_28 | 0 | - | - | - | | 32 | 44 | VDDIO\_2 | DI/DO | GPIO\_28 | 1 | - | SPI\_SS | SPI Slave Select | | 32 | 44 | VDDIO\_2 | DI/DO | GPIO\_28 | 2 | - | - | - | | 32 | 44 | VDDIO\_2 | DI/DO | GPIO\_28 | 3 | - | I2S\_BCLK | I^2^S Bit Clock | | 32 | 44 | VDDIO\_2 | DI/DO | GPIO\_28 | 4 | - | - | - | | 32 | 44 | VDDIO\_2 | DI/DO | GPIO\_28 | 5 | - | I2C0\_SCL | I^2^C 0 Serial Clock | | 32 | 44 | VDDIO\_2 | DI/DO | GPIO\_28 | 6 | - | I2C1\_SCL | I^2^C 1 Serial Clock | | 32 | 44 | VDDIO\_2 | DI/DO | GPIO\_28 | 7 | uart\_sig\_4\_sel=0 | UART0\_RTS | UART 0 Request To Send | | 32 | 44 | VDDIO\_2 | DI/DO | GPIO\_28 | 7 | uart\_sig\_4\_sel=1 | UART0\_CTS | UART 0 Clear To Send | | 32 | 44 | VDDIO\_2 | DI/DO | GPIO\_28 | 7 | uart\_sig\_4\_sel=2 | UART0\_TXD | UART 0 Transmit Data | | 32 | 44 | VDDIO\_2 | DI/DO | GPIO\_28 | 7 | uart\_sig\_4\_sel=3 | UART0\_RXD | UART 0 Receive Data | | 32 | 44 | VDDIO\_2 | DI/DO | GPIO\_28 | 7 | uart\_sig\_4\_sel=4 | UART1\_RTS | UART 1 Request To Send | | 32 | 44 | VDDIO\_2 | DI/DO | GPIO\_28 | 7 | uart\_sig\_4\_sel=5 | UART1\_CTS | UART 1 Clear To Send | | 32 | 44 | VDDIO\_2 | DI/DO | GPIO\_28 | 7 | uart\_sig\_4\_sel=6 | UART1\_TXD | UART 1 Transmit Data | | 32 | 44 | VDDIO\_2 | DI/DO | GPIO\_28 | 7 | uart\_sig\_4\_sel=7 | UART1\_RXD | UART 1 Receive Data | | 32 | 44 | VDDIO\_2 | DI/DO | GPIO\_28 | 7 | uart\_sig\_4\_sel=8 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 32 | 44 | VDDIO\_2 | DI/DO | GPIO\_28 | 7 | uart\_sig\_4\_sel=9 | - | - | | 32 | 44 | VDDIO\_2 | DI/DO | GPIO\_28 | 7 | uart\_sig\_4\_sel=10 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 32 | 44 | VDDIO\_2 | DI/DO | GPIO\_28 | 7 | uart\_sig\_4\_sel=11 | ISO11898\_RXD | CAN (ISO 11898) Receive Data | | 32 | 44 | VDDIO\_2 | DI/DO | GPIO\_28 | 8 | - | RMII\_RXD[0] | RMII Receive Data [0] (QCC744) | | 32 | 44 | VDDIO\_2 | DI/DO | GPIO\_28 | 9 | - | CAM0\_HSYNC | Camera 0 Horizontal Sync (QCC744) | | 32 | 44 | VDDIO\_2 | DI/DO | GPIO\_28 | 10 | - | - | - | | 32 | 44 | VDDIO\_2 | DI/DO | GPIO\_28 | 11 | - | SWGPIO28 | Software GPIO 28 | | 32 | 44 | VDDIO\_2 | DI/DO | GPIO\_28 | 12 | - | - | - | | 32 | 44 | VDDIO\_2 | DI/DO | GPIO\_28 | 16 | reg\_pwm1\_io\_sel=0 | PWM0\_CH0P | PWM 0 Channel 0 Positive | | 32 | 44 | VDDIO\_2 | DI/DO | GPIO\_28 | 16 | reg\_pwm1\_io\_sel=1 | PWM0\_CH2P | PWM 0 Channel 2 Positive | | 32 | 44 | VDDIO\_2 | DI/DO | GPIO\_28 | 22 | - | - | - | | 32 | 44 | VDDIO\_2 | DI/DO | GPIO\_28 | 23 | - | - | - | | 32 | 44 | VDDIO\_2 | DI/DO | GPIO\_28 | 24 | - | - | - | | 32 | 44 | VDDIO\_2 | DI/DO | GPIO\_28 | 25 | - | AUDAC\_PWM\_P | AUDAC\_PWM\_P | | 32 | 44 | VDDIO\_2 | DI/DO | GPIO\_28 | 26 | - | M0\_JTAG\_TMS | M0 JTAG Test Mode Select | | 33 | 45 | VDDIO\_2 | DI/DO | GPIO\_29 | 0 | - | - | - | | 33 | 45 | VDDIO\_2 | DI/DO | GPIO\_29 | 1 | - | SPI\_SCLK | SPI Serial Clock | | 33 | 45 | VDDIO\_2 | DI/DO | GPIO\_29 | 2 | - | - | - | | 33 | 45 | VDDIO\_2 | DI/DO | GPIO\_29 | 3 | - | I2S\_FS | I^2^S Frame Sync | | 33 | 45 | VDDIO\_2 | DI/DO | GPIO\_29 | 4 | - | - | - | | 33 | 45 | VDDIO\_2 | DI/DO | GPIO\_29 | 5 | - | I2C0\_SDA | I^2^C 0 Serial Data | | 33 | 45 | VDDIO\_2 | DI/DO | GPIO\_29 | 6 | - | I2C1\_SDA | I^2^C 1 Serial Data | | 33 | 45 | VDDIO\_2 | DI/DO | GPIO\_29 | 7 | uart\_sig\_5\_sel=0 | UART0\_RTS | UART 0 Request To Send | | 33 | 45 | VDDIO\_2 | DI/DO | GPIO\_29 | 7 | uart\_sig\_5\_sel=1 | UART0\_CTS | UART 0 Clear To Send | | 33 | 45 | VDDIO\_2 | DI/DO | GPIO\_29 | 7 | uart\_sig\_5\_sel=2 | UART0\_TXD | UART 0 Transmit Data | | 33 | 45 | VDDIO\_2 | DI/DO | GPIO\_29 | 7 | uart\_sig\_5\_sel=3 | UART0\_RXD | UART 0 Receive Data | | 33 | 45 | VDDIO\_2 | DI/DO | GPIO\_29 | 7 | uart\_sig\_5\_sel=4 | UART1\_RTS | UART 1 Request To Send | | 33 | 45 | VDDIO\_2 | DI/DO | GPIO\_29 | 7 | uart\_sig\_5\_sel=5 | UART1\_CTS | UART 1 Clear To Send | | 33 | 45 | VDDIO\_2 | DI/DO | GPIO\_29 | 7 | uart\_sig\_5\_sel=6 | UART1\_TXD | UART 1 Transmit Data | | 33 | 45 | VDDIO\_2 | DI/DO | GPIO\_29 | 7 | uart\_sig\_5\_sel=7 | UART1\_RXD | UART 1 Receive Data | | 33 | 45 | VDDIO\_2 | DI/DO | GPIO\_29 | 7 | uart\_sig\_5\_sel=8 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 33 | 45 | VDDIO\_2 | DI/DO | GPIO\_29 | 7 | uart\_sig\_5\_sel=9 | - | - | | 33 | 45 | VDDIO\_2 | DI/DO | GPIO\_29 | 7 | uart\_sig\_5\_sel=10 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 33 | 45 | VDDIO\_2 | DI/DO | GPIO\_29 | 7 | uart\_sig\_5\_sel=11 | ISO11898\_RXD | CAN (ISO 11898) Receive Data | | 33 | 45 | VDDIO\_2 | DI/DO | GPIO\_29 | 8 | - | RMII\_RXD[1] | RMII Receive Data [1] (QCC744) | | 33 | 45 | VDDIO\_2 | DI/DO | GPIO\_29 | 9 | - | CAM0\_VSYNC | Camera 0 Vertical Sync (QCC744) | | 33 | 45 | VDDIO\_2 | DI/DO | GPIO\_29 | 10 | - | - | - | | 33 | 45 | VDDIO\_2 | DI/DO | GPIO\_29 | 11 | - | SWGPIO29 | Software GPIO 29 | | 33 | 45 | VDDIO\_2 | DI/DO | GPIO\_29 | 12 | - | - | - | | 33 | 45 | VDDIO\_2 | DI/DO | GPIO\_29 | 16 | reg\_pwm1\_io\_sel=0 | PWM0\_CH1P | PWM 0 Channel 1 Positive | | 33 | 45 | VDDIO\_2 | DI/DO | GPIO\_29 | 16 | reg\_pwm1\_io\_sel=1 | PWM0\_CH2N | PWM 0 Channel 2 Negative | | 33 | 45 | VDDIO\_2 | DI/DO | GPIO\_29 | 22 | - | - | - | | 33 | 45 | VDDIO\_2 | DI/DO | GPIO\_29 | 23 | - | - | - | | 33 | 45 | VDDIO\_2 | DI/DO | GPIO\_29 | 24 | - | - | - | | 33 | 45 | VDDIO\_2 | DI/DO | GPIO\_29 | 25 | - | - | - | | 33 | 45 | VDDIO\_2 | DI/DO | GPIO\_29 | 26 | - | M0\_JTAG\_TCK | M0 JTAG Test Clock | | 34 | 46 | VDDIO\_2 | DI/DO | GPIO\_30 | 0 | - | - | - | | 34 | 46 | VDDIO\_2 | DI/DO | GPIO\_30 | 1 | - | SPI\_MISO | SPI Master Input, Slave Output | | 34 | 46 | VDDIO\_2 | DI/DO | GPIO\_30 | 2 | - | - | - | | 34 | 46 | VDDIO\_2 | DI/DO | GPIO\_30 | 3 | - | I2S\_DI/I2S\_RCLK\_O | I^2^S Data Input/I^2^S Receive Clock Output | | 34 | 46 | VDDIO\_2 | DI/DO | GPIO\_30 | 4 | - | - | - | | 34 | 46 | VDDIO\_2 | DI/DO | GPIO\_30 | 5 | - | I2C0\_SCL | I^2^C 0 Serial Clock | | 34 | 46 | VDDIO\_2 | DI/DO | GPIO\_30 | 6 | - | I2C1\_SCL | I^2^C 1 Serial Clock | | 34 | 46 | VDDIO\_2 | DI/DO | GPIO\_30 | 7 | uart\_sig\_6\_sel=0 | UART0\_RTS | UART 0 Request To Send | | 34 | 46 | VDDIO\_2 | DI/DO | GPIO\_30 | 7 | uart\_sig\_6\_sel=1 | UART0\_CTS | UART 0 Clear To Send | | 34 | 46 | VDDIO\_2 | DI/DO | GPIO\_30 | 7 | uart\_sig\_6\_sel=2 | UART0\_TXD | UART 0 Transmit Data | | 34 | 46 | VDDIO\_2 | DI/DO | GPIO\_30 | 7 | uart\_sig\_6\_sel=3 | UART0\_RXD | UART 0 Receive Data | | 34 | 46 | VDDIO\_2 | DI/DO | GPIO\_30 | 7 | uart\_sig\_6\_sel=4 | UART1\_RTS | UART 1 Request To Send | | 34 | 46 | VDDIO\_2 | DI/DO | GPIO\_30 | 7 | uart\_sig\_6\_sel=5 | UART1\_CTS | UART 1 Clear To Send | | 34 | 46 | VDDIO\_2 | DI/DO | GPIO\_30 | 7 | uart\_sig\_6\_sel=6 | UART1\_TXD | UART 1 Transmit Data | | 34 | 46 | VDDIO\_2 | DI/DO | GPIO\_30 | 7 | uart\_sig\_6\_sel=7 | UART1\_RXD | UART 1 Receive Data | | 34 | 46 | VDDIO\_2 | DI/DO | GPIO\_30 | 7 | uart\_sig\_6\_sel=8 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 34 | 46 | VDDIO\_2 | DI/DO | GPIO\_30 | 7 | uart\_sig\_6\_sel=9 | - | - | | 34 | 46 | VDDIO\_2 | DI/DO | GPIO\_30 | 7 | uart\_sig\_6\_sel=10 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 34 | 46 | VDDIO\_2 | DI/DO | GPIO\_30 | 7 | uart\_sig\_6\_sel=11 | ISO11898\_RXD | CAN (ISO 11898) Receive Data | | 34 | 46 | VDDIO\_2 | DI/DO | GPIO\_30 | 8 | - | RMII\_RXERR | RMII Receive Error (QCC744) | | 34 | 46 | VDDIO\_2 | DI/DO | GPIO\_30 | 9 | - | CAM0\_CLK | Camera 0 Clock (QCC744) | | 34 | 46 | VDDIO\_2 | DI/DO | GPIO\_30 | 10 | - | AUADC\_CH7 | Audio ADC Channel 7 (QCC744) | | 34 | 46 | VDDIO\_2 | DI/DO | GPIO\_30 | 11 | - | SWGPIO30 | Software GPIO 30 | | 34 | 46 | VDDIO\_2 | DI/DO | GPIO\_30 | 12 | - | - | - | | 34 | 46 | VDDIO\_2 | DI/DO | GPIO\_30 | 16 | reg\_pwm1\_io\_sel=0 | PWM0\_CH2P | PWM 0 Channel 2 Positive | | 34 | 46 | VDDIO\_2 | DI/DO | GPIO\_30 | 16 | reg\_pwm1\_io\_sel=1 | PWM0\_CH3P | PWM 0 Channel 3 Positive | | 34 | 46 | VDDIO\_2 | DI/DO | GPIO\_30 | 22 | - | - | - | | 34 | 46 | VDDIO\_2 | DI/DO | GPIO\_30 | 23 | - | - | - | | 34 | 46 | VDDIO\_2 | DI/DO | GPIO\_30 | 24 | - | - | - | | 34 | 46 | VDDIO\_2 | DI/DO | GPIO\_30 | 25 | - | - | - | | 34 | 46 | VDDIO\_2 | DI/DO | GPIO\_30 | 26 | - | M0\_JTAG\_TDO | M0 JTAG Test Data Out | | - | 47 | VDDIO\_2 | DI/DO | GPIO\_31 | 0 | - | - | - | | - | 47 | VDDIO\_2 | DI/DO | GPIO\_31 | 1 | - | SPI\_MOSI | SPI Master Output, Slave Input | | - | 47 | VDDIO\_2 | DI/DO | GPIO\_31 | 2 | - | - | - | | - | 47 | VDDIO\_2 | DI/DO | GPIO\_31 | 3 | - | I2S\_DO/I2S\_RCLK\_O | I^2^S Data Output/I^2^S Receive Clock
Output | | - | 47 | VDDIO\_2 | DI/DO | GPIO\_31 | 4 | - | - | - | | - | 47 | VDDIO\_2 | DI/DO | GPIO\_31 | 5 | - | I2C0\_SDA | I^2^C 0 Serial Data | | - | 47 | VDDIO\_2 | DI/DO | GPIO\_31 | 6 | - | I2C1\_SDA | I^2^C 1 Serial Data | | - | 47 | VDDIO\_2 | DI/DO | GPIO\_31 | 7 | uart\_sig\_7\_sel=0 | UART0\_RTS | UART 0 Request To Send | | - | 47 | VDDIO\_2 | DI/DO | GPIO\_31 | 7 | uart\_sig\_7\_sel=1 | UART0\_CTS | UART 0 Clear To Send | | - | 47 | VDDIO\_2 | DI/DO | GPIO\_31 | 7 | uart\_sig\_7\_sel=2 | UART0\_TXD | UART 0 Transmit Data | | - | 47 | VDDIO\_2 | DI/DO | GPIO\_31 | 7 | uart\_sig\_7\_sel=3 | UART0\_RXD | UART 0 Receive Data | | - | 47 | VDDIO\_2 | DI/DO | GPIO\_31 | 7 | uart\_sig\_7\_sel=4 | UART1\_RTS | UART 1 Request To Send | | - | 47 | VDDIO\_2 | DI/DO | GPIO\_31 | 7 | uart\_sig\_7\_sel=5 | UART1\_CTS | UART 1 Clear To Send | | - | 47 | VDDIO\_2 | DI/DO | GPIO\_31 | 7 | uart\_sig\_7\_sel=6 | UART1\_TXD | UART 1 Transmit Data | | - | 47 | VDDIO\_2 | DI/DO | GPIO\_31 | 7 | uart\_sig\_7\_sel=7 | UART1\_RXD | UART 1 Receive Data | | - | 47 | VDDIO\_2 | DI/DO | GPIO\_31 | 7 | uart\_sig\_7\_sel=8 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | - | 47 | VDDIO\_2 | DI/DO | GPIO\_31 | 7 | uart\_sig\_7\_sel=9 | - | - | | - | 47 | VDDIO\_2 | DI/DO | GPIO\_31 | 7 | uart\_sig\_7\_sel=10 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | - | 47 | VDDIO\_2 | DI/DO | GPIO\_31 | 7 | uart\_sig\_7\_sel=11 | ISO11898\_RXD | CAN (ISO 11898) Receive Data | | - | 47 | VDDIO\_2 | DI/DO | GPIO\_31 | 8 | - | RMII\_TX\_EN | RMII Transmit Enable (QCC744) | | - | 47 | VDDIO\_2 | DI/DO | GPIO\_31 | 9 | - | CAM0\_DAT4 | Camera 0 Data 4 (QCC744) | | - | 47 | VDDIO\_2 | DI/DO | GPIO\_31 | 10 | - | - | - | | - | 47 | VDDIO\_2 | DI/DO | GPIO\_31 | 11 | - | SWGPIO31 | Software GPIO 31 | | - | 47 | VDDIO\_2 | DI/DO | GPIO\_31 | 12 | - | - | - | | - | 47 | VDDIO\_2 | DI/DO | GPIO\_31 | 16 | reg\_pwm1\_io\_sel=0 | PWM0\_CH3P | PWM 0 Channel 3 Positive | | - | 47 | VDDIO\_2 | DI/DO | GPIO\_31 | 16 | reg\_pwm1\_io\_sel=1 | PWM0\_CH3N | PWM 0 Channel 3 Negative | | - | 47 | VDDIO\_2 | DI/DO | GPIO\_31 | 22 | - | - | - | | - | 47 | VDDIO\_2 | DI/DO | GPIO\_31 | 23 | - | - | - | | - | 47 | VDDIO\_2 | DI/DO | GPIO\_31 | 24 | - | - | - | | - | 47 | VDDIO\_2 | DI/DO | GPIO\_31 | 25 | - | - | - | | - | 47 | VDDIO\_2 | DI/DO | GPIO\_31 | 26 | - | M0\_JTAG\_TDI | M0 JTAG Test Data Input | | - | 48 | VDDIO\_2 | DI/DO | GPIO\_32 | 0 | - | - | - | | - | 48 | VDDIO\_2 | DI/DO | GPIO\_32 | 1 | - | SPI\_SS | SPI Slave Select | | - | 48 | VDDIO\_2 | DI/DO | GPIO\_32 | 2 | - | - | - | | - | 48 | VDDIO\_2 | DI/DO | GPIO\_32 | 3 | - | I2S\_BCLK | I^2^S Bit Clock | | - | 48 | VDDIO\_2 | DI/DO | GPIO\_32 | 4 | - | - | - | | - | 48 | VDDIO\_2 | DI/DO | GPIO\_32 | 5 | - | I2C0\_SCL | I^2^C 0 Serial Clock | | - | 48 | VDDIO\_2 | DI/DO | GPIO\_32 | 6 | - | I2C1\_SCL | I^2^C 1 Serial Clock | | - | 48 | VDDIO\_2 | DI/DO | GPIO\_32 | 7 | uart\_sig\_8\_sel=0 | UART0\_RTS | UART 0 Request To Send | | - | 48 | VDDIO\_2 | DI/DO | GPIO\_32 | 7 | uart\_sig\_8\_sel=1 | UART0\_CTS | UART 0 Clear To Send | | - | 48 | VDDIO\_2 | DI/DO | GPIO\_32 | 7 | uart\_sig\_8\_sel=2 | UART0\_TXD | UART 0 Transmit Data | | - | 48 | VDDIO\_2 | DI/DO | GPIO\_32 | 7 | uart\_sig\_8\_sel=3 | UART0\_RXD | UART 0 Receive Data | | - | 48 | VDDIO\_2 | DI/DO | GPIO\_32 | 7 | uart\_sig\_8\_sel=4 | UART1\_RTS | UART 1 Request To Send | | - | 48 | VDDIO\_2 | DI/DO | GPIO\_32 | 7 | uart\_sig\_8\_sel=5 | UART1\_CTS | UART 1 Clear To Send | | - | 48 | VDDIO\_2 | DI/DO | GPIO\_32 | 7 | uart\_sig\_8\_sel=6 | UART1\_TXD | UART 1 Transmit Data | | - | 48 | VDDIO\_2 | DI/DO | GPIO\_32 | 7 | uart\_sig\_8\_sel=7 | UART1\_RXD | UART 1 Receive Data | | - | 48 | VDDIO\_2 | DI/DO | GPIO\_32 | 7 | uart\_sig\_8\_sel=8 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | - | 48 | VDDIO\_2 | DI/DO | GPIO\_32 | 7 | uart\_sig\_8\_sel=9 | - | - | | - | 48 | VDDIO\_2 | DI/DO | GPIO\_32 | 7 | uart\_sig\_8\_sel=10 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | - | 48 | VDDIO\_2 | DI/DO | GPIO\_32 | 7 | uart\_sig\_8\_sel=11 | ISO11898\_RXD | CAN (ISO 11898) Receive Data | | - | 48 | VDDIO\_2 | DI/DO | GPIO\_32 | 8 | - | RMII\_RX\_DV | RMII Receive Data Valid (QCC744) | | - | 48 | VDDIO\_2 | DI/DO | GPIO\_32 | 9 | - | CAM0\_DAT5 | Camera 0 Data 5 (QCC744) | | - | 48 | VDDIO\_2 | DI/DO | GPIO\_32 | 10 | - | - | - | | - | 48 | VDDIO\_2 | DI/DO | GPIO\_32 | 11 | - | SWGPIO32 | Software GPIO 32 | | - | 48 | VDDIO\_2 | DI/DO | GPIO\_32 | 12 | - | - | - | | - | 48 | VDDIO\_2 | DI/DO | GPIO\_32 | 16 | reg\_pwm1\_io\_sel=0 | PWM0\_CH0P | PWM 0 Channel 0 Positive | | - | 48 | VDDIO\_2 | DI/DO | GPIO\_32 | 16 | reg\_pwm1\_io\_sel=1 | PWM0\_CH0P | PWM 0 Channel 0 Positive | | - | 48 | VDDIO\_2 | DI/DO | GPIO\_32 | 22 | - | - | - | | - | 48 | VDDIO\_2 | DI/DO | GPIO\_32 | 23 | - | - | - | | - | 48 | VDDIO\_2 | DI/DO | GPIO\_32 | 24 | - | - | - | | - | 48 | VDDIO\_2 | DI/DO | GPIO\_32 | 25 | - | - | - | | - | 48 | VDDIO\_2 | DI/DO | GPIO\_32 | 26 | - | M0\_JTAG\_TMS | M0 JTAG Test Mode Select | | - | 49 | VDDIO\_2 | DI/DO | GPIO\_33 | 0 | - | - | - | | - | 49 | VDDIO\_2 | DI/DO | GPIO\_33 | 1 | - | SPI\_SCLK | SPI Serial Clock | | - | 49 | VDDIO\_2 | DI/DO | GPIO\_33 | 2 | - | - | - | | - | 49 | VDDIO\_2 | DI/DO | GPIO\_33 | 3 | - | I2S\_FS | I^2^S Frame Sync | | - | 49 | VDDIO\_2 | DI/DO | GPIO\_33 | 4 | - | - | - | | - | 49 | VDDIO\_2 | DI/DO | GPIO\_33 | 5 | - | I2C0\_SDA | I^2^C 0 Serial Data | | - | 49 | VDDIO\_2 | DI/DO | GPIO\_33 | 6 | - | I2C1\_SDA | I^2^C 1 Serial Data | | - | 49 | VDDIO\_2 | DI/DO | GPIO\_33 | 7 | uart\_sig\_9\_sel=0 | UART0\_RTS | UART 0 Request To Send | | - | 49 | VDDIO\_2 | DI/DO | GPIO\_33 | 7 | uart\_sig\_9\_sel=1 | UART0\_CTS | UART 0 Clear To Send | | - | 49 | VDDIO\_2 | DI/DO | GPIO\_33 | 7 | uart\_sig\_9\_sel=2 | UART0\_TXD | UART 0 Transmit Data | | - | 49 | VDDIO\_2 | DI/DO | GPIO\_33 | 7 | uart\_sig\_9\_sel=3 | UART0\_RXD | UART 0 Receive Data | | - | 49 | VDDIO\_2 | DI/DO | GPIO\_33 | 7 | uart\_sig\_9\_sel=4 | UART1\_RTS | UART 1 Request To Send | | - | 49 | VDDIO\_2 | DI/DO | GPIO\_33 | 7 | uart\_sig\_9\_sel=5 | UART1\_CTS | UART 1 Clear To Send | | - | 49 | VDDIO\_2 | DI/DO | GPIO\_33 | 7 | uart\_sig\_9\_sel=6 | UART1\_TXD | UART 1 Transmit Data | | - | 49 | VDDIO\_2 | DI/DO | GPIO\_33 | 7 | uart\_sig\_9\_sel=7 | UART1\_RXD | UART 1 Receive Data | | - | 49 | VDDIO\_2 | DI/DO | GPIO\_33 | 7 | uart\_sig\_9\_sel=8 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | - | 49 | VDDIO\_2 | DI/DO | GPIO\_33 | 7 | uart\_sig\_9\_sel=9 | - | - | | - | 49 | VDDIO\_2 | DI/DO | GPIO\_33 | 7 | uart\_sig\_9\_sel=10 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | - | 49 | VDDIO\_2 | DI/DO | GPIO\_33 | 7 | uart\_sig\_9\_sel=11 | ISO11898\_RXD | CAN (ISO 11898) Receive Data | | - | 49 | VDDIO\_2 | DI/DO | GPIO\_33 | 8 | - | RMII\_MDC | RMII Management Data Clock (QCC744) | | - | 49 | VDDIO\_2 | DI/DO | GPIO\_33 | 9 | - | CAM0\_DAT6 | Camera 0 Data 6 (QCC744) | | - | 49 | VDDIO\_2 | DI/DO | GPIO\_33 | 10 | - | - | - | | - | 49 | VDDIO\_2 | DI/DO | GPIO\_33 | 11 | - | SWGPIO33 | Software GPIO 33 | | - | 49 | VDDIO\_2 | DI/DO | GPIO\_33 | 12 | - | - | - | | - | 49 | VDDIO\_2 | DI/DO | GPIO\_33 | 16 | reg\_pwm1\_io\_sel=0 | PWM0\_CH1P | PWM 0 Channel 1 Positive | | - | 49 | VDDIO\_2 | DI/DO | GPIO\_33 | 16 | reg\_pwm1\_io\_sel=1 | PWM0\_CH0N | PWM 0 Channel 0 Negative | | - | 49 | VDDIO\_2 | DI/DO | GPIO\_33 | 22 | - | - | - | | - | 49 | VDDIO\_2 | DI/DO | GPIO\_33 | 23 | - | - | - | | - | 49 | VDDIO\_2 | DI/DO | GPIO\_33 | 24 | - | - | - | | - | 49 | VDDIO\_2 | DI/DO | GPIO\_33 | 25 | - | - | - | | - | 49 | VDDIO\_2 | DI/DO | GPIO\_33 | 26 | - | M0\_JTAG\_TCK | M0 JTAG Test Clock | | - | 50 | VDDIO\_2 | DI/DO | GPIO\_34 | 0 | - | - | - | | - | 50 | VDDIO\_2 | DI/DO | GPIO\_34 | 1 | - | SPI\_MISO | SPI Master Input, Slave Output | | - | 50 | VDDIO\_2 | DI/DO | GPIO\_34 | 2 | - | - | - | | - | 50 | VDDIO\_2 | DI/DO | GPIO\_34 | 3 | - | I2S\_DI/I2S\_RCLK\_O | I^2^S Data Input/I^2^S Receive Clock Output | | - | 50 | VDDIO\_2 | DI/DO | GPIO\_34 | 4 | - | - | - | | - | 50 | VDDIO\_2 | DI/DO | GPIO\_34 | 5 | - | I2C0\_SCL | I^2^C 0 Serial Clock | | - | 50 | VDDIO\_2 | DI/DO | GPIO\_34 | 6 | - | I2C1\_SCL | I^2^C 1 Serial Clock | | - | 50 | VDDIO\_2 | DI/DO | GPIO\_34 | 7 | uart\_sig\_10\_sel=0 | UART0\_RTS | UART 0 Request To Send | | - | 50 | VDDIO\_2 | DI/DO | GPIO\_34 | 7 | uart\_sig\_10\_sel=1 | UART0\_CTS | UART 0 Clear To Send | | - | 50 | VDDIO\_2 | DI/DO | GPIO\_34 | 7 | uart\_sig\_10\_sel=2 | UART0\_TXD | UART 0 Transmit Data | | - | 50 | VDDIO\_2 | DI/DO | GPIO\_34 | 7 | uart\_sig\_10\_sel=3 | UART0\_RXD | UART 0 Receive Data | | - | 50 | VDDIO\_2 | DI/DO | GPIO\_34 | 7 | uart\_sig\_10\_sel=4 | UART1\_RTS | UART 1 Request To Send | | - | 50 | VDDIO\_2 | DI/DO | GPIO\_34 | 7 | uart\_sig\_10\_sel=5 | UART1\_CTS | UART 1 Clear To Send | | - | 50 | VDDIO\_2 | DI/DO | GPIO\_34 | 7 | uart\_sig\_10\_sel=6 | UART1\_TXD | UART 1 Transmit Data | | - | 50 | VDDIO\_2 | DI/DO | GPIO\_34 | 7 | uart\_sig\_10\_sel=7 | UART1\_RXD | UART 1 Receive Data | | - | 50 | VDDIO\_2 | DI/DO | GPIO\_34 | 7 | uart\_sig\_10\_sel=8 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | - | 50 | VDDIO\_2 | DI/DO | GPIO\_34 | 7 | uart\_sig\_10\_sel=9 | - | - | | - | 50 | VDDIO\_2 | DI/DO | GPIO\_34 | 7 | uart\_sig\_10\_sel=10 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | - | 50 | VDDIO\_2 | DI/DO | GPIO\_34 | 7 | uart\_sig\_10\_sel=11 | ISO11898\_RXD | CAN (ISO 11898) Receive Data | | - | 50 | VDDIO\_2 | DI/DO | GPIO\_34 | 8 | - | RMII\_MDIO | RMII Management Data Input/Output (QCC744) | | - | 50 | VDDIO\_2 | DI/DO | GPIO\_34 | 9 | - | CAM0\_DAT7 | Camera 0 Data 7 (QCC744) | | - | 50 | VDDIO\_2 | DI/DO | GPIO\_34 | 10 | - | - | - | | - | 50 | VDDIO\_2 | DI/DO | GPIO\_34 | 11 | - | SWGPIO34 | Software GPIO 34 | | - | 50 | VDDIO\_2 | DI/DO | GPIO\_34 | 12 | - | - | - | | - | 50 | VDDIO\_2 | DI/DO | GPIO\_34 | 16 | reg\_pwm1\_io\_sel=0 | PWM0\_CH2P | PWM 0 Channel 2 Positive | | - | 50 | VDDIO\_2 | DI/DO | GPIO\_34 | 16 | reg\_pwm1\_io\_sel=1 | PWM0\_CH1P | PWM 0 Channel 1 Positive | | - | 50 | VDDIO\_2 | DI/DO | GPIO\_34 | 22 | - | - | - | | - | 50 | VDDIO\_2 | DI/DO | GPIO\_34 | 23 | - | - | - | | - | 50 | VDDIO\_2 | DI/DO | GPIO\_34 | 24 | - | - | - | | - | 50 | VDDIO\_2 | DI/DO | GPIO\_34 | 25 | - | - | - | | - | 50 | VDDIO\_2 | DI/DO | GPIO\_34 | 26 | - | M0\_JTAG\_TDO | M0 JTAG Test Data Out | | 35 | 51 | AVDD33\_RF3 | Clock | XTAL\_IN | - | - | XTAL\_IN | - | | 36 | 52 | AVDD33\_RF3 | Clock | XTAL\_OUT | - | - | XTAL\_OUT | - | | 37 | 53 | - | Power, Input | AVDD33\_RF3 | - | - | AVDD33\_RF3 | 3.3 V power supply of RF transceiver | | 38 | 54 | - | Power, Input | AVDD18\_RF | - | - | AVDD18\_RF | 1.8 V power supply of RF transceiver | | 39 | 55 | - | Power, Output | AVDD15\_RF2 | - | - | AVDD15\_RF2 | 1.5 V power supply of RF transceiver (internal regulator
output) | | 40 | 56 | - | Power, Input | AVDD15\_RF1 | - | - | AVDD15\_RF1 | 1.5 V power supply of RF transceiver | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Note: - Only one of CAM0 and CAM1 can be selected. - When selected as the SPI function, the default is SPI\_MISO, which can be converted to SPI\_MOSI through the register. ### Pin mux table Source: [https://docs.qualcomm.com/doc/80-WL743-1/topic/pin-definitions.html](https://docs.qualcomm.com/doc/80-WL743-1/topic/pin-definitions.html) | QCC743 | QCC744 | GPIO | Voltage | QSPI | Serial Flash | SDIO Slave | SDIO Master | SPI | I^2^C
0/1 | UART
0/1 | I^2^S | PWM | CAN (ISO11898) | Audio
ADC | Audio
DAC | EMAC | DVP | MIPI-DBI | JTAG | | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | | 4 | 4 | GPIO0 | VDDIO1 | - | - | - | - | CS | SCL | RTS/CTS/TX/RX | BCLK | CH0P/CH0P | TX/RX | CH9 | - | - | CAM1\_

VSYNC | - | TMS | | 5 | 5 | GPIO1 | VDDIO1 | - | - | - | - | CLK | SDA | RTS/CTS/TX/RX | FS | CH1P/CH0N | TX/RX | CH8 | - | - | CAM1\_

HSYNC | - | TCK | | 6 | 6 | GPIO2 | VDDIO1 | - | - | - | - | MISO | SCL | RTS/CTS/TX/RX | DI | CH2P/CH1P | TX/RX | CH2 | - | - | | - | TDO | | 7 | 7 | GPIO3 | VDDIO1 | - | - | - | - | MOSI | SDA | RTS/CTS/TX/RX | DO | CH3P/CH1N | TX/RX | CH3 | - | - | CAM1\_

DAT0 | - | TDI | | - | 8 | GPIO4 | VDDIO1 | SCL | SF2\_CS | - | - | CS | SCL | RTS/CTS/TX/RX | BCLK | CH0P/CH2P | TX/RX | - | - | - | | B\_WRn/C\_SCL | TMS | | - | 9 | GPIO5 | VDDIO1 | CS | SF2\_D1 | - | - | CLK | SDA | RTS/CTS/TX/RX | FS | CH1P/CH2N | TX/RX | - | - | - | - | B\_CSn/C\_CSn | TCK | | - | 10 | GPIO6 | VDDIO1 | SDA0 | SF2\_D2 | - | - | MISO | SCL | RTS/CTS/TX/RX | DI | CH2P/CH3P | TX/RX | - | - | - | - | B\_RDn/C\_SDA0 | TDO | | - | 11 | GPIO7 | VDDIO1 | SDA1 | SF2\_D0 | - | - | MOSI | SDA | RTS/CTS/TX/RX | DO | CH3P/CH3N | TX/RX | - | - | - | - | B\_DCn/C\_DCn | TDI | | - | 12 | GPIO8 | VDDIO1 | SDA2 | SF2\_CLK | - | - | CS | SCL | RTS/CTS/TX/RX | BCLK | CH0P/CH0P | TX/RX | - | - | - | - | B\_DB0/C\_SCL | TMS | | - | 14 | GPIO9 | VDDIO1 | SDA3 | SF2\_D3 | - | - | CLK | SDA | RTS/CTS/TX/RX | FS | CH1P/CH0N | TX/RX | - | - | - | - | B\_DB1/C\_CSn | TCK | | 9 | 15 | GPIO10 | VDDIO1 | SCL | SF3\_D3 | DAT2 | DAT1 | MISO | SCL | RTS/CTS/TX/RX | DI | CH2P/CH1P | TX/RX | CH7 | - | - | CAM1\_

DAT1 | B\_DB2/C\_SDA0 | TDO | | 10 | 16 | GPIO11 | VDDIO1 | CS | SF3\_CLK | DAT3 | DAT0 | MOSI | SDA | RTS/CTS/TX/RX | DO | CH3P/CH1N | TX/RX | - | - | - | CAM1\_

DAT2 | B\_DB3/C\_DCn | TDI | | 11 | 17 | GPIO12 | VDDIO1 | SDA0 | SF3\_D0 | CMD | CLK | CS | SCL | RTS/CTS/TX/RX | BCLK | CH0P/CH2P | TX/RX | CH6 | - | - | CAM1\_

DAT3 | B\_DB4/C\_SCL | TMS | | 12 | 18 | GPIO13 | VDDIO1 | SDA1 | SF3\_D2 | CLK | CMD | CLK | SDA | RTS/CTS/TX/RX | FS | CH1P/CH2N | TX/RX | CH5 | - | - | CAM1\_

CLK | B\_DB5/C\_CSn | TCK | | 13 | 19 | GPIO14 | VDDIO1 | SDA2 | SF3\_D1 | DAT0 | DAT3 | MISO | SCL | RTS/CTS/TX/RX | DI | CH2P/CH3P | TX/RX | CH4 | A\_PWM\_P | - | CAM1\_

DAT4 | B\_DB6/C\_SDA0 | TDO | | 14 | 20 | GPIO15 | VDDIO1 | SDA3 | SF3\_CS | DAT1 | DAT2 | MOSI | SDA | RTS/CTS/TX/RX | DO | CH3P/CH3N | TX/RX | - | A\_PWM\_N | - | CAM1\_

DAT5 | B\_DB7/C\_DCn | TDI | | 15 | 21 | GPIO16 | VDD33 | - | - | - | - | CS | SCL | RTS/CTS/TX/RX | BCLK | CH0P/CH0P | TX/RX | - | - | - | CAM1\_

DAT6 | - | TMS | | 16 | 22 | GPIO17 | VDD33 | - | - | - | - | CLK | SDA | RTS/CTS/TX/RX | FS | CH1P/CH0N | TX/RX | - | - | | CAM1\_

DAT7 | - | TCK | | - | 24 | GPIO19 | VDD33 | - | - | - | - | MOSI | SDA | RTS/CTS/TX/RX | DO | CH3P/CH1N | TX/RX | CH1 | - | - | - | - | TDI | | 27 | 35 | GPIO20 | VDDIO2 | - | - | - | - | CS | SCL | RTS/CTS/TX/RX | BCLK | CH0P/CH2P | TX/RX | CH0/A\_CH0 | - | - | - | - | TMS | | 28 | 36 | GPIO21 | VDDIO2 | - | - | - | - | CLK | SDA | RTS/CTS/TX/RX | FS | CH1P/CH2N | TX/RX | AU\_CH1 | - | - | - | - | TCK | | 29 | 37 | GPIO22 | VDDIO2 | - | - | - | - | MISO | SCL | RTS/CTS/TX/RX | DI | CH2P/CH3P | TX/RX | AU\_CH2 | A\_PWM\_P | - | - | - | TDO | | - | 38 | GPIO23 | VDDIO2 | - | - | - | - | MOSI | SDA | RTS/CTS/TX/RX | DO | CH3P/CH3N | TX/RX | AU\_CH3 | A\_PWM\_N | - | - | - | TDI | | - | 39 | GPIO24 | VDDIO2 | - | - | - | - | CS | SCL | RTS/CTS/TX/RX | BCLK | CH0P/CH0P | TX/RX | - | - | - | CAM0\_

DAT0 | - | TMS | | - | 40 | GPIO25 | VDDIO2 | - | - | - | - | CLK | SDA | RTS/CTS/TX/RX | FS | CH1P/CH0N | TX/RX | - | - | REF\_CLK | CAM0\_

DAT1 | - | TCK | | - | 41 | GPIO26 | VDDIO2 | - | - | - | - | MISO | SCL | RTS/CTS/TX/RX | DI | CH2P/CH1P | TX/RX | - | - | TXD[0] | CAM0\_

DAT2 | - | TDO | | 31 | 43 | GPIO27 | VDDIO2 | - | - | - | - | MOSI | SDA | RTS/CTS/TX/RX | DO | CH3P/CH1N | TX/RX | CH10/A\_CH4 | A\_PWM\_N | TXD[1] | CAM0\_

DAT3 | - | TDI | | 32 | 44 | GPIO28 | VDDIO2 | - | - | - | - | CS | SCL | RTS/CTS/TX/RX | BCLK | CH0P/CH2P | TX/RX | CH11/A\_CH5 | A\_PWM\_P | RXD[0] | CAM0\_

HSYNC | - | TMS | | 33 | 45 | GPIO29 | VDDIO2 | - | - | - | - | CLK | SDA | RTS/CTS/TX/RX | FS | CH1P/CH2N | TX/RX | AU\_CH6 | - | RXD[1] | CAM0\_

VSYNC | - | TCK | | 34 | 46 | GPIO30 | VDDIO2 | - | - | - | - | MISO | SCL | RTS/CTS/TX/RX | DI | CH2P/CH3P | TX/RX | AU\_CH7 | - | RXERR | CAM0\_

CLK | - | TDO | | - | 47 | GPIO31 | VDDIO2 | - | - | - | - | MOSI | SDA | RTS/CTS/TX/RX | DO | CH3P/CH3N | TX/RX | - | - | TX\_EN | CAM0\_

DAT4 | - | TDI | | - | 48 | GPIO32 | VDDIO2 | - | - | - | - | CS | SCL | RTS/CTS/TX/RX | BCLK | CH0P/CH0P | TX/RX | - | - | RX\_DV | CAM0\_

DAT5 | - | TMS | | - | 49 | GPIO33 | VDDIO2 | - | - | - | - | CLK | SDA | RTS/CTS/TX/RX | FS | CH1P/CH0N | TX/RX | - | - | MDC | CAM0\_

DAT6 | - | TCK | | - | 50 | GPIO34 | VDDIO2 | - | - | - | - | MISO | SCL | RTS/CTS/TX/RX | DI | CH2P/CH1P | TX/RX | - | - | MDIO | CAM0\_

DAT7 | - | TDO | Table : QCC744 GPIOs for external flash connection | Pin number | Pin name | Main function | Voltage domain | Type | Peripheral internal function select | Description | | --- | --- | --- | --- | --- | --- | --- | | 8 | GPIO\_4 | CS | VDDIO\_1 | DI/DO | Serial flash\_CS | Serial flash chip select | | 9 | GPIO\_5 | SO | VDDIO\_1 | DI/DO | Serial flash\_D1 | Serial flash Data 1 | | 10 | GPIO\_6 | WP | VDDIO\_1 | DI/DO | Serial flash\_D2 | Serial flash Data 2 | | 11 | GPIO\_7 | SI | VDDIO\_1 | DI/DO | Serial flash\_D0 | Serial flash Data 0 | | 12 | GPIO\_8 | SCLK | VDDIO\_1 | DI/DO | Serial flash\_CLK | Serial flash Clock | | 14 | GPIO\_9 | HOLD | VDDIO\_1 | DI/DO | Serial flash\_D3 | Serial flash Data 3 | Table : QCC743 GPIOs for external flash connection | Pin number | Pin name | Main function | Voltage domain | Type | Peripheral internal function select | Description | | --- | --- | --- | --- | --- | --- | --- | | 9 | GPIO\_10 | HOLD | VDDIO\_1 | DI/DO | Serial flash\_D3 | Serial flash data 3 | | 10 | GPIO\_11 | SCLK | VDDIO\_1 | DI/DO | Serial flash\_CLK | Serial flash clock | | 11 | GPIO\_12 | SI | VDDIO\_1 | DI/DO | Serial flash\_D0 | Serial flash data 0 | | 12 | GPIO\_13 | WP | VDDIO\_1 | DI/DO | Serial flash\_D2 | Serial flash data 2 | | 13 | GPIO\_14 | SO | VDDIO\_1 | DI/DO | Serial flash\_D1 | Serial flash data 1 | | 14 | GPIO\_15 | CS | VDDIO\_1 | DI/DO | Serial flash\_CS | Serial flash chip select | Last Published: Apr 22, 2026 [Previous Topic Introduction](https://docs.qualcomm.com/bundle/publicresource/80-WL743-1/topics/introduction.md) [Next Topic Electrical specifications](https://docs.qualcomm.com/bundle/publicresource/80-WL743-1/topics/electrical-specifications.md)