# Introduction
Source: [https://docs.qualcomm.com/doc/80-WL748-1/topic/introduction.html](https://docs.qualcomm.com/doc/80-WL748-1/topic/introduction.html)
Technical information for the QCC748 is primarily covered by the
documents listed in [Table : Primary QCC748 documentation](https://docs.qualcomm.com/doc/80-WL748-1/topic/introduction.html#introduction__table_drk_mdv_yzb). Each is a self-contained
document, but a thorough understanding of the device and its applications requires
familiarization with all of them. The device description is a good place to start. All
released documents are posted at Qualcomm technical support website [https://qualcomm.com/support](https://qualcomm.com/support) and are
available for download.
Table : Primary QCC748 documentation
| Document number | Title |
| --- | --- |
| 80-WL748-1 | QCC748 Data Sheet |
The data sheet is organized as follows:
| Chapter | Description |
| --- | --- |
| Chapter 1 | Gives a high-level functional description of the device, lists the device features, and defines marking conventions, terms, and acronyms used throughout this document. |
| Chapter 2 | Defines the device pin assignments. |
| Chapter 3 | Defines the device electrical characteristics, including absolute maximum ratings and recommended operating conditions. |
| Chapter 4 | Provides IC mechanical information, including dimensions, markings, ordering information, moisture sensitivity, and thermal characteristics. |
| Chapter 5 | Describes carrier, storage, and handling information of the QCC748 |
| Chapter 6 | Presents procedures and specifications for mounting the QCC748 onto printed circuit boards (PCBs). |
| Chapter 7 | Presents QCC748 reliability data, including a definition of the qualification samples and a summary of qualification |
| Chapter 8 | Describes known issues of the device. |
## Functional block diagram
Source: [https://docs.qualcomm.com/doc/80-WL748-1/topic/introduction.html](https://docs.qualcomm.com/doc/80-WL748-1/topic/introduction.html)
Figure : QCC748 functional block diagram
Note: See [Table : 3. Ordering information](https://docs.qualcomm.com/doc/80-WL748-1/topic/mechanical-information.html#device-ordering-information__table_qnc_b3l_c1c) for more information about built-in pSRAM and flash support options.
## QCC748 features
Source: [https://docs.qualcomm.com/doc/80-WL748-1/topic/introduction.html](https://docs.qualcomm.com/doc/80-WL748-1/topic/introduction.html)
Some hardware features of QCC748 must be enabled by software. See the
latest software release notes for the enabled features.
Table : QCC748 features
| Feature | QCC748capability |
| --- | --- |
| Wireless (Tier-1 RF performance) |
2.4 GHz RF transceiver
Wi-Fi 6 (IEEE 802.11 b/g/n/ax)
BLE v5.4
IEEE 802.15.4 (Thread and Zigbee-ready)
Wi-Fi fast connection with BLE assistance
Wi-Fi/BLE/802.15.4 coexistence
Wi-Fi security WPS/WEP/WPA/WPA2/WPA3
Wi-Fi 20/40 MHz bandwidth, 1T1R, up to 229.4 Mbps
LDPC, STBC, beamformee, DL/UL OFDMA, MU-MIMO, Target Wake Time (TWT), Spatial Reuse (SR), Dual Carrier Modulation (DCM), Extended Range (ER)
A-MPDU, A-MSDU, immediate block ACK, fragmentation, and defragmentation
|
## Functional description
Source: [https://docs.qualcomm.com/doc/80-WL748-1/topic/introduction.html](https://docs.qualcomm.com/doc/80-WL748-1/topic/introduction.html)
QCC748 has two buses: AXI and AHB. ROM, flash and pSRAM are on the AXI
bus, allowing high-speed access to memories. Peripherals are connected to the CPU
through the AHB bus.
Figure : QCC748 system architecture
### CPU
Source: [https://docs.qualcomm.com/doc/80-WL748-1/topic/introduction.html](https://docs.qualcomm.com/doc/80-WL748-1/topic/introduction.html)
QCC748 has a built-in 32‑bit RISC-V CPU, which adopts a 5-stage pipeline
structure for fetch, decode, execute, memory access, and writeback. QCC748 supports RISC-V 32/16‑bit mixed instruction set, and includes 64
external interrupt sources. Interrupt priority can be configured through 4 bits.
### Cache
Source: [https://docs.qualcomm.com/doc/80-WL748-1/topic/introduction.html](https://docs.qualcomm.com/doc/80-WL748-1/topic/introduction.html)
QCC748 includes a 32 KB instruction cache and a 16 KB data cache to
improve external memory access performance.
### Memory
Source: [https://docs.qualcomm.com/doc/80-WL748-1/topic/introduction.html](https://docs.qualcomm.com/doc/80-WL748-1/topic/introduction.html)
QCC748 includes an on-chip zero-delay SRAM memory, a read-only memory, a
write-once memory, built-in flash (optional), and built-in pSRAM (optional).
### DMA
Source: [https://docs.qualcomm.com/doc/80-WL748-1/topic/introduction.html](https://docs.qualcomm.com/doc/80-WL748-1/topic/introduction.html)
The DMA controller has four dedicated channels to manage data transfers between
peripherals and memory to improve CPU/bus efficiency. DMA has four transfer types:
memory-to-memory, memory-to-peripheral, peripheral-to-memory, and
peripheral-to-peripheral.
The DMA controller supports the Linked List Item (LLI) feature, which consists of lists
of pre-defined multiple transfers. Hardware automatically completes all transfers based
on the size and address of each LLI.
The following peripherals support DMA:
- UART
- I^2^C
- I^2^S
- SPI
- Audio ADC and DAC
- GPIO
- DBI
- GPADC and GPDAC
### Memory map
Source: [https://docs.qualcomm.com/doc/80-WL748-1/topic/introduction.html](https://docs.qualcomm.com/doc/80-WL748-1/topic/introduction.html)
OCRAM and WRAM can be accessed through either AHB or AXI bus. When the CPU accesses the
OCRAM through the 0x62FC0000 base address, it goes through the internal cache and
accesses the OCRAM through AXI to AHB. When the CPU accesses the OCRAM through the
0x22FC0000 base address, it accesses the OCRAM through the AHB bus directly.
| Module | Size | Base address | Base address |
| --- | --- | --- | --- |
| Module | Size | Cache | Non-cached |
| OCRAM | 320 KB | 0x62FC0000 | 0x22FC0000 |
| WRAM | 160 KB | 0x63010000 | 0x23010000 |
| | | | |
| Module | Target | Base address | Size | Description |
| --- | --- | --- | --- | --- |
| FLASH | Flash | 0xA0000000 | 128 MB | Application address space |
| pSRAM | pSRAM | 0xA8000000 | 128 MB | pSRAM memory address space (optional) |
| RAM | HBNRAM | 0x20010000 | 4 KB | HBN RAM, mainly used for data saving in ultralow power mode |
| Peripheral | USB | 0x20072000 | 4 KB | USB High-Speed control register |
| Peripheral | EMAC | 0x20070000 | 4 KB | EMAC control register |
| Peripheral | SDH | 0x20060000 | 4 KB | SDH control register |
| Peripheral | MJPEG | 0x20059000 | 4 KB | MJPEG control register |
| Peripheral | DVP | 0x20057000 | 4 KB | DVP camera interface control register |
| Peripheral | eFuse | 0x20056000 | 4 KB | eFuse storage control register |
| Peripheral | Audio DAC | 0x20055000 | 4 KB | Audio PWM control register |
| Peripheral | PSRAM\_Ctrl | 0x20052000 | 4 KB | pSRAM control register |
| Peripheral | HBN | 0x2000F000 | 4 KB | Hibernate register |
| Peripheral | PDS | 0x2000E000 | 4 KB | Power-down sleep register |
| Peripheral | SDU | 0x2000D000 | 4 KB | SDU control register |
| Peripheral | DMA | 0x2000C000 | 4 KB | DMA control register |
| Peripheral | SF\_Ctrl | 0x2000B000 | 4 KB | Serial Flash control register |
| Peripheral | Audio ADC | 0x2000AC00 | 256 B | Audio ADC control register |
| Peripheral | I^2^S | 0x2000AB00 | 256 B | I^2^S control register |
| Peripheral | CAN (ISO 11898) | 0x2000AA00 | 256 B | CAN (ISO 11898) control register |
| Peripheral | I^2^C1 | 0x2000A900 | 256 B | I^2^C1 control register |
| Peripheral | Display | 0x2000A800 | 256 B | Display control register |
| Peripheral | IRR | 0x2000A600 | 256 B | IR receiver control register |
| Peripheral | TIMER | 0x2000A500 | 256 B | Timer control register |
| Peripheral | PWM | 0x2000A400 | 256 B | PWM control register |
| Peripheral | I^2^C0 | 0x2000A300 | 256 B | I^2^C0 control register |
| Peripheral | SPI | 0x2000A200 | 256 B | SPI control register |
| Peripheral | UART1 | 0x2000A100 | 256 B | UART1 control register |
| Peripheral | UART0 | 0x2000A000 | 256 B | UART0 control register |
| Peripheral | TZ | 0x20005000 | 4 KB | TrustZone control register |
| Peripheral | SEC\_ENG | 0x20004000 | 4 KB | Security engine control register |
| Peripheral | GPIP | 0x20002000 | 1 KB | General purpose DAC/ADC/ACOMP interface control register |
| Peripheral | GLB | 0x20000000 | 4 KB | Global control register |
| ROM | ROM | 0x90000000 | 128 KB | Boot ROM address space |
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### Interrupt
Source: [https://docs.qualcomm.com/doc/80-WL748-1/topic/introduction.html](https://docs.qualcomm.com/doc/80-WL748-1/topic/introduction.html)
QCC748 supports internal RTC clock and external interrupt to enable
low-power sleep/wake-up function.
The CPU interrupt controller supports 64 maskable interrupt trigger sources for UART,
I^2^C, SPI, timer, and DMA.
All I/O pins can be configured to external interrupt input mode, which supports the
following trigger types:
- Synchronous high/low-level trigger
- Synchronous rising/falling edge trigger
- Asynchronous high/low-level trigger
- Asynchronous rising edge/falling edge trigger
- Synchronous double edge trigger
### Boot
Source: [https://docs.qualcomm.com/doc/80-WL748-1/topic/introduction.html](https://docs.qualcomm.com/doc/80-WL748-1/topic/introduction.html)
QCC748 supports boot options from UART, SDU, or Flash.
| Boot pin | Level | Description |
| --- | --- | --- |
| GPIO2 | 1 | Boot from UART (GPIO21/22)/SDU. This mode is mainly used for flash programming or downloading image to RAM for execution (wireless transparent transmission scenario) |
| GPIO2 | 0 | Launch application image from Flash. |
| | | |
Note:
Boot from USB isn't supported, that is, downloading image from USB isn't
supported.
### Power
Source: [https://docs.qualcomm.com/doc/80-WL748-1/topic/introduction.html](https://docs.qualcomm.com/doc/80-WL748-1/topic/introduction.html)
PMU manages the power of the entire chip with 5 modes: running, idle, sleep, hibernation,
and power off. The system can be configured to enter or exit sleep mode by software
using the RTC timer or EINT for low-power sleep and accurate wake-up management. The
power-down sleep modes can be used to enable lowest power consumption applications.
### Clock
Source: [https://docs.qualcomm.com/doc/80-WL748-1/topic/introduction.html](https://docs.qualcomm.com/doc/80-WL748-1/topic/introduction.html)
The clock control unit generates the clocks to the CPU and the peripheral devices. The
root clock source can be an XTAL, PLL, or RC oscillator. Dynamic power-saving is enabled
by configurations such as sel, div, en.
Figure : Clock architecture
### Peripheral
Source: [https://docs.qualcomm.com/doc/80-WL748-1/topic/introduction.html](https://docs.qualcomm.com/doc/80-WL748-1/topic/introduction.html)
QCC748's peripherals include GPIO, UART, SPI,
I^2^C, PWM, Timer, IR (Rx), Display (DBI/QSPI), I^2^S, Audio
(Audio ADC+Audio DAC), SDU, DVP, MJPEG, SD/MMC (SDH), Ethernet MAC, GPDAC, GPADC, ACOMP,
and USB 2.0.
### GPIO
Source: [https://docs.qualcomm.com/doc/80-WL748-1/topic/introduction.html](https://docs.qualcomm.com/doc/80-WL748-1/topic/introduction.html)
QCC748has up to
35 GPIOs with the following
features:
- Each GPIO can be used as a general-purpose input and output. Pull-up, pull-down,
float can be configured by software.
- Each GPIO supports an interrupt function with the following trigger mode:
- Synchronous high/low-level trigger
- Synchronous rising/falling edge trigger
- Asynchronous high/low-level trigger
- Asynchronous rising/falling edge trigger
- Synchronous double edge trigger
- Each GPIO can be set to high-impedance state for low-power modes.
### UART
Source: [https://docs.qualcomm.com/doc/80-WL748-1/topic/introduction.html](https://docs.qualcomm.com/doc/80-WL748-1/topic/introduction.html)
QCC748has two built-in Universal Asynchronous Serial Transceivers
(UART) with the following features:
- CTS and RTS flow control in hardware
- LIN master/slave function
- Configurable data bits, stop bits, and parity bits
- Automatic baud rate detection for common/fixed characters
- Selectable working clock (FCLK, XCLK, or 160 MHz)
- 10 Mbps baud rate maximum
- Independent FIFO of 32 bytes depth for Tx and Rx
- DMA function support
### SPI
Source: [https://docs.qualcomm.com/doc/80-WL748-1/topic/introduction.html](https://docs.qualcomm.com/doc/80-WL748-1/topic/introduction.html)
QCC748has a built-in SPI which can be configured as Master or Slave
mode. The SPI module clock is XCLK or 160 MHz, with the following characteristics:
- Up to 40 MHz clock frequency in Master mode
- Up to 40 MHz Master clock frequency in Slave mode
- Configurable frame bit width: 8‑bit, 16‑bit, 24‑bit, or 32‑bit.
- Adaptive FIFO depth for high-performance applications:
- Bit width = 32‑bit, FIFO depth = 8 bytes
- Bit width = 24‑bit, FIFO depth = 8 bytes
- Bit width = 16‑bit, FIFO depth = 16 bytes
- Bit width = 8‑bit, FIFO depth = 32 bytes
- Supports DMA transfer mode
The SPI timing diagram is shown below:
Figure : SPI slave mode timing diagram
Table : SPI slave mode timing characteristic value
| Symbol | Description | Min | Max | Unit |
| :---: | --- | :---: | :---: | :---: |
| Tcyc | CLK clock period | 25[^1^](https://docs.qualcomm.com/doc/80-WL748-1/topic/introduction.html#fntarg_1_spi) | - | ns |
| Tsuss | Setup Time SPI\_SS valid before first clock edge | 10 | **-** | ns |
| Thss | Hold Time SPI\_SS valid after last clock edge | 10 | - | ns |
| Ts | MOSI setup time | 6 | - | ns |
| Th | MOSI hold time | 6 | - | ns |
| Tvld | MOSI output delay | - | 8 | ns |
[^1^](https://docs.qualcomm.com/doc/80-WL748-1/topic/introduction.html#fnsrc_1_spi) SPI core clock should run at 80MHz.
### I^2^C
Source: [https://docs.qualcomm.com/doc/80-WL748-1/topic/introduction.html](https://docs.qualcomm.com/doc/80-WL748-1/topic/introduction.html)
QCC748 has two built-in I^2^C interfaces with the following
features:
- Multi-master mode and arbitration function
- Selectable working clock (BCLK or XCLK)
- Selectable register address length (1 byte, 2 bytes, 3 bytes, 4 bytes)
- Independent transceiver FIFO of 2-word depth
- Supports DMA function
### EMAC
Source: [https://docs.qualcomm.com/doc/80-WL748-1/topic/introduction.html](https://docs.qualcomm.com/doc/80-WL748-1/topic/introduction.html)
The 10/100 Mbps Ethernet Media Access Controller (EMAC) module is compatible with
IEEE 802.3 standard, with the following features:
- MAC layer compatible with IEEE 802.3
- PHY supporting MII/RMII interface defined by IEEE 802.3
- Interaction with PHY through MDIO interface
- 10 Mbps and 100 Mbps Ethernet
- Half-duplex and full-duplex
- Automatic flow control and control frame generation in full-duplex mode
- Collision detection and retransmission in half-duplex mode
- CRC generation and verification
- Data frame preamble generation and removal
- Automatic extension of short data frames at sending
- Too long/short data frames (length limit) detection
- Long data frames (> standard Ethernet frame length) transmission
- Automatic data packets discard on overlimit retransmission times or small
frame gap
- Broadcast packet filtering
- Internal RAM for storing up to 128 BDs
- Data packet splitting to multiple consecutive BDs at sending
- Various event flags for sent or received packet
- Interrupt generation upon event
The EMAC timing diagram is shown in the following figure.
Figure : EMAC timing diagram
Set the corresponding bit of register eth\_cfg0 when using Rx clock:
- cfg\_inv\_eth\_rx\_clk = 1
- cfg\_inv\_eth\_tx\_clk = 0
- cfg\_sel\_eth\_ref\_clk\_o = 0
| Timing parameters (1.8 V, Load = 20 pF) | Timing parameters (1.8 V, Load = 20 pF) | Min. | Typ | Max. | Unit | Note |
| --- | --- | --- | --- | --- | --- | --- |
| Tcyc | Clock cycle | - | 20 | - | ns | Clock from ETH PHY |
| Tvld | Output valid delay | 6.98 | - | 15.63 | ns | TXD/TX\_EN |
| Tsu | Input setup time | 11.64 | - | - | ns | RXD/RX\_DV/RXERR |
| Th | Input hold time | 0 | - | - | ns | RXD/RX\_DV/RXERR |
Set the corresponding bit of register eth\_cfg0 when not using Rx clock:
- cfg\_inv\_eth\_rx\_clk = 0
- cfg\_inv\_eth\_tx\_clk = 0
- cfg\_sel\_eth\_ref\_clk\_o = 0
| Timing parameters (1.8 V, Load = 20 pF) | Timing parameters (1.8 V, Load = 20 pF) | Min. | Typ | Max. | Unit | Note |
| --- | --- | --- | --- | --- | --- | --- |
| Tcyc | Clock cycle | - | 20 | - | ns | Clock from ETH PHY |
| Tvld | Output valid delay | 6.98 | - | 15.63 | ns | TXD/TX\_EN |
| Tsu | Input setup time | 3.5 | - | - | ns | RXD/RX\_DV/RXERR |
| Th | Input hold time | 2 | - | - | ns | RXD/RX\_DV/RXERR |
### I^2^S
Source: [https://docs.qualcomm.com/doc/80-WL748-1/topic/introduction.html](https://docs.qualcomm.com/doc/80-WL748-1/topic/introduction.html)
QCC748 has a built-in I^2^S interface with the following
features:
- Master mode and slave mode support
- Using audio PLL for working clock
- 4-channel and 6-channel modes in addition to mono/dual-channel mode
- Playback of mono audio dubbing to binaural mode
- Dynamic mute switching function
- Independent transceiver FIFO of 16-word depth
- DMA function support
### CAN (ISO 11898)
Source: [https://docs.qualcomm.com/doc/80-WL748-1/topic/introduction.html](https://docs.qualcomm.com/doc/80-WL748-1/topic/introduction.html)
QCC748has a built-in CAN (ISO 11898) controller with the following
features:
- 1 Mbps and custom bit rate
- Self-test mode (self-sending and self-receiving)
- Silent mode (no reply, no valid error flag)
- Single or reliable transmission
- Standard and extended frame
- 0 bytes to 8 bytes transmission
- Bit querying of arbitration lose
- Configurable (one or two) filters
### Timer
Source: [https://docs.qualcomm.com/doc/80-WL748-1/topic/introduction.html](https://docs.qualcomm.com/doc/80-WL748-1/topic/introduction.html)
QCC748has two built-in 32-bit general purpose timers and one 16-bit
watchdog timer with the following features:
- Selectable clock source of the general purpose timer: FCLK, 32K, XTAL
- Selectable clock source of the watchdog timer: FCLK, 32K, XTAL.
- 8-bit divider for each counter
- 3 compare registers for each group of general-purpose timers
- Supports compare interrupts
- Supports FreeRun mode and PreLoad mode in counting mode
- Watchdog overflow modes: interrupt or reset
### PWM
Source: [https://docs.qualcomm.com/doc/80-WL748-1/topic/introduction.html](https://docs.qualcomm.com/doc/80-WL748-1/topic/introduction.html)
QCC748has a built-in group of PWM signals. Each group has a 4-channel
PWM signal output. Each channel can be set to 2-channel complementary PWM with the
following characteristics:
- Selectable clock source (BCLK, XCLK, 32K) with 16-bit clock divider
- Independent period configuration for each group of PWM
- Dual threshold settings for each channel PWM, allowing different duty cycles and
phases for increased pulse elasticity
- Independent dead time setting for each channel PWM
- Each PWM output pin can be set to a different active level
- Each PWM has an independent connection switch to select whether to connect to
the internal counter or not, and to set the default output level when not
connected
- Brake signal can put the PWM output level into a preset state
- Up to 11 trigger sources for triggering ADC conversion
- Interrupt types: counter overflow interrupt, threshold value comparison
interrupt, cycle count interrupt
### IR
Source: [https://docs.qualcomm.com/doc/80-WL748-1/topic/introduction.html](https://docs.qualcomm.com/doc/80-WL748-1/topic/introduction.html)
QCC748has a built-in Infrared Remote (IR) controller with the following
features:
- Supports fixed protocols NEC, RC-5 for data receiving, in any format with pulse
width counting
- The clock source is XCLK. The maximum operating frequency is 40 MHz
- Supports up to 64-bit data bits
- Receive FIFO of 128 bytes depth
- Supports receive end interrupt
### Audio ADC
Source: [https://docs.qualcomm.com/doc/80-WL748-1/topic/introduction.html](https://docs.qualcomm.com/doc/80-WL748-1/topic/introduction.html)
QCC748 has one integrated 1-channel audio ADC (can't be used
simultaneously with the high precision ADC) with the following features:
- Sampling rate: 8k to 96k
- Signal-to-noise ratio (A-W): 96 dB at 6 dB gain, at 48k sampling rate
- Harmonic distortion + noise: -90 dB at 6 dB gain, at 48k sampling rate
- Analog preamp gain: 6 dB to 42 dB, in 3 dB steps
- Analog fully differential or single-ended input
- Adjustable high pass filter and digital volume control
- PDM interface support (one-way DMIC)
- Input signal multiplexing GPIO
- Transmit FIFO width of 32‑bit, depth of 8
- Supports DMA transfer mode
### Audio DAC
Source: [https://docs.qualcomm.com/doc/80-WL748-1/topic/introduction.html](https://docs.qualcomm.com/doc/80-WL748-1/topic/introduction.html)
QCC748 has one integrated 1-channel audio DAC with the following
features:
- Sampling rate: 8k to 48k
- Signal to noise ratio (A-W): 95 dB at 48k sampling rate
- Harmonic distortion + noise: -80 dB at 48k sampling rate
- Adjustable digital volume control
- Differential complementary outputs support
- Output signal multiplexing
- Transmit FIFO width of 32‑bit, depth of 16
- Supports DMA transfer mode
### GPADC
Source: [https://docs.qualcomm.com/doc/80-WL748-1/topic/introduction.html](https://docs.qualcomm.com/doc/80-WL748-1/topic/introduction.html)
QCC748has a built-in 12‑bit successive approximation Analog-to-Digital
Converter (ADC) with the following features.
- Up to 2 M sampling rate for single-channel continuous conversion mode
- Up to 500 K sampling rate for other conversion modes
- 12 external analog channels
- Conversion modes:
- Single-channel single conversion
- Single-channel continuous conversion
- Multichannel single conversion
- Multichannel continuous conversion
- 2.0 V/3.2 V selectable internal reference voltage, 12/14/16 bits (using
oversampling) left-aligned conversion results
- 32-byte deep FIFO
- Multiple interrupt support
- DMA support
- Application examples:
- Supply voltage measurement in addition to common analog signal
measurements
- Temperature detection by measuring internal/external diode voltages
### High precision ADC
Source: [https://docs.qualcomm.com/doc/80-WL748-1/topic/introduction.html](https://docs.qualcomm.com/doc/80-WL748-1/topic/introduction.html)
QCC748 has a built-in 1-channel high precision ADC (can't be used
simultaneously with audio codec) with the following features:
- Fully differential input, 4 channels
- Effective Resolution (ER): 19.5 bit
- Programmable gain amplifier: 6 dB to 42 dB (2 to 128x), in 3 dB steps
- Programmable data rates: 20 SPS, 100 SPS, 200 SPS, 400 SPS, 1000 SPS, 2000 SPS
- High accuracy/low latency dual set digital filters
- 50 Hz/60 Hz simultaneous frequency suppression
- Software global chopping, ER = 20.7 bit, below 1 μV offset voltage
- Multiplexed GPIO input signals
- Transmit FIFO of 32-bit width and 8 bytes depth
- Polling, interrupt, and DMA transfer modes support
### SDIO
Source: [https://docs.qualcomm.com/doc/80-WL748-1/topic/introduction.html](https://docs.qualcomm.com/doc/80-WL748-1/topic/introduction.html)
SDIO timing is shown in the following diagrams:
Figure : SDIO input timing
Figure : SDIO output timing
| Symbol | Parameter | Remark | Min. | Typ | Max. | Unit |
| --- | --- | --- | --- | --- | --- | --- |
| Clock CLK (all values are referred to min (VIH) and max (VIL)) | Clock CLK (all values are referred to min (VIH) and max (VIL)) | Clock CLK (all values are referred to min (VIH) and max (VIL)) | Clock CLK (all values are referred to min (VIH) and max (VIL)) | Clock CLK (all values are referred to min (VIH) and max (VIL)) | Clock CLK (all values are referred to min (VIH) and max (VIL)) | Clock CLK (all values are referred to min (VIH) and max (VIL)) |
| f PP | Clock frequency data transfer mode | CCARD≤ 10 pF (1 card) | 0 | – | 50 | MHz |
| tWL | Clock low time | CCARD≤ 10 pF (1 card) | 7 | – | – | ns |
| tWH | Clock high time | CCARD≤ 10 pF (1 card) | 7 | – | – | ns |
| tTLH | Clock rise time | CCARD≤ 10 pF (1 card) | – | – | 3 | ns |
| tTHL | Clock fall time | CCARD≤ 10 pF (1 card) | – | – | 3 | ns |
| Inputs CMD, DAT (referenced to CLK) | Inputs CMD, DAT (referenced to CLK) | Inputs CMD, DAT (referenced to CLK) | Inputs CMD, DAT (referenced to CLK) | Inputs CMD, DAT (referenced to CLK) | Inputs CMD, DAT (referenced to CLK) | Inputs CMD, DAT (referenced to CLK) |
| tISU | Input set-up time | CCARD≤ 10 pF (1 card) | 6 | – | – | ns |
| tIH | Input hold time | CCARD≤ 10 pF (1 card) | 2 | – | – | ns |
| Outputs CMD, DAT (referenced to CLK) | Outputs CMD, DAT (referenced to CLK) | Outputs CMD, DAT (referenced to CLK) | Outputs CMD, DAT (referenced to CLK) | Outputs CMD, DAT (referenced to CLK) | Outputs CMD, DAT (referenced to CLK) | Outputs CMD, DAT (referenced to CLK) |
| tODLY | Output delay time during data transfer mode | CL≤ 40 pF (1 card) | – | – | 14 | ns |
| tOH | Output hold time | CL≥ 15 pF (1 card) | 2.5 | – | – | ns |
| CL | Total system capacitance for each line [^1^](https://docs.qualcomm.com/doc/80-WL748-1/topic/introduction.html#fntarg_1_sdio) | 1 card | – | – | 40 | pF |
[^1^](https://docs.qualcomm.com/doc/80-WL748-1/topic/introduction.html#fnsrc_1_sdio) To satisfy stringent
timing, the host shall drive one card only.
## Device variants
Source: [https://docs.qualcomm.com/doc/80-WL748-1/topic/introduction.html](https://docs.qualcomm.com/doc/80-WL748-1/topic/introduction.html)
Table : QCC748 supported features and peripherals
| Device | QCC748 |
| :---: | --- |
| CPU | E907 |
| I-Cache | 32 KB |
| D-Cache | 16 KB |
| SRAM | 484 KB |
| pSRAM | Optional |
| eFuse | 4 Kb |
| ROM | 128 KB |
| Flash | Optional |
| UART | 2 |
| CAN (ISO 11898) | 1 |
| SPI | 1 |
| EMAC | ✓ |
| SDIO Slave | ✓ |
| SDIO Host | ✓ |
| I^2^C | 2 |
| I^2^S | 1 |
| PWM | 1 PWM (4 channels with complementary outputs) |
| GPADC | 12 channels |
| GPDAC | ✓ (GPIO2/3) |
| ACOMP | ✓ |
| GPIO | 35 |
| DMA | ✓ |
| GLB | ✓ |
| PDS | ✓ |
| HBN | ✓ |
| MJPEG | ✓ |
| SECENG | ✓ |
| Display | ✓ |
| CAM | ✓ |
| Audio DAC | ✓ |
| Audio ADC | ✓ |
| Timer | ✓ |
| IR (Rx) | ✓ (GPIO9-23) |
| USB | ✓ |
## Terms and acronyms
Source: [https://docs.qualcomm.com/doc/80-WL748-1/topic/introduction.html](https://docs.qualcomm.com/doc/80-WL748-1/topic/introduction.html)
The following table defines terms and acronyms commonly used throughout this
document.
Table : Terms and acronyms
| Term | Definition |
| --- | --- |
| ACOMP | Analog comparator |
| AHB | Advanced high-performance bus |
| A-MPDU | Aggregate MAC protocol data unit |
| A-MSDU | Aggregate MAC service data unit |
| APC | Automatic power control |
| AXI | Advanced extensible interface |
| BLE | Bluetooth low energy |
| DBI | Data bus interface |
| DEVM | Differential error vector magnitude |
| DTIM | Delivery traffic indication map |
| DSP | Digital signal processor |
| DVP | Digital video port |
| EVM | Error vector magnitude |
| FPU | Floating point unit |
| GPADC | General purpose analog-to-digital converter |
| GPDAC | General purpose digital-to-analog converter |
| HBM | Human body model |
| HBN | Hibernate |
| LDPC | Low density parity check |
| MIPI | Mobile industry processor interface |
| MMC | Multimedia card |
| OCRAM | On-chip RAM |
| OLPC | Open loop power control |
| PDS | Power-down sleep |
| PGA | Programmable gain amplifiers |
| pSRAM | Pseudo static random access memory |
| PMU | Power management unit |
| PWM | Pulse-width modulation |
| QSPI | Quad serial peripheral interface |
| RMS | Root mean square |
| SDU | Service data unit |
| SDH | Synchronous digital hierarchy |
| SiP | System in package |
| SNR | Signal-to-noise ratio |
| STBC | Space time block code |
| THD | Total harmonic distortion |
| TPC | Transmit power control |
| TCM | Tightly-coupled memory |
| WEP | Wired equivalent privacy |
| WPA | Wi-Fi protected access |
| WPS | Wi-Fi protected setup |
| WMM | Wi-Fi multi-media |
Last Published: Apr 22, 2026
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