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# Pin definitions Source: [https://docs.qualcomm.com/doc/80-WL748-1/topic/pin-definitions.html](https://docs.qualcomm.com/doc/80-WL748-1/topic/pin-definitions.html) ## I/O parameter definitions Source: [https://docs.qualcomm.com/doc/80-WL748-1/topic/pin-definitions.html](https://docs.qualcomm.com/doc/80-WL748-1/topic/pin-definitions.html) | **Symbol** | **Description** | | --- | --- | | ***Pin attribute*** | ***Pin attribute*** | | AI | Analog input (does not include pin circuitry) | | AO | Analog output (does not include pin circuitry) | | B | Bidirectional digital with CMOS input | | DI | Digital input (CMOS) | | DO | Digital output (CMOS) | | H | High-voltage tolerant | | S | Schmitt trigger input | | Z | High-impedance (Hi-Z) output | | ***Pin pull details for digital I/Os*** | ***Pin pull details for digital I/Os*** | | nppdpukp | Programmable pull resistor. The default pull direction is indicated
using capital letters, and is a prefix to other programmable options:

NP: pdpukp = default no-pull, with programmable options following
the colon (:)

PD: nppukp = default pull-down, with
programmable options following the colon (:)

PU: nppdkp =
default pull-up, with programmable options following the colon
(:)

KP: nppdpu = default keeper, with programmable options
following the colon (:) | | KP | Contains an internal weak keeper device (keepers cannot drive
external buses) | | NP | Contains no internal pull | | PU | Contains an internal pull-up device | | PD | Contains an internal pull-down device | ## Pin assignments Source: [https://docs.qualcomm.com/doc/80-WL748-1/topic/pin-definitions.html](https://docs.qualcomm.com/doc/80-WL748-1/topic/pin-definitions.html) ### Pin map QCC748 56-pin package includes 15 fixed power ports, 4 fixed analog ports, and up to 35 configurable GPIO ports. ### Pin descriptions Source: [https://docs.qualcomm.com/doc/80-WL748-1/topic/pin-definitions.html](https://docs.qualcomm.com/doc/80-WL748-1/topic/pin-definitions.html) | QCC748 | Voltage domain | Type | Pin name | GPIO function select number | Peripheral internal function select | PAD main function | Description | | --- | --- | --- | --- | --- | --- | --- | --- | | 1 | AVDD15\_RF1 | Analog | ANT | - | - | ANT | RF signal pin | | 2 | - | Power, Input | AVDD33\_RF1 | - | - | AVDD33\_RF1 | RF transmitter power supply, 3.3 V | | 3 | - | Power, Input | AVDD33\_RF2 | - | - | AVDD33\_RF2 | RF transmitter power supply, 3.3 V | | 4 | VDDIO\_1 | DI/DO | GPIO\_0 | 0 | - | - | - | | 4 | VDDIO\_1 | DI/DO | GPIO\_0 | 1 | - | SPI\_SS | SPI Slave Select | | 4 | VDDIO\_1 | DI/DO | GPIO\_0 | 2 | - | - | - | | 4 | VDDIO\_1 | DI/DO | GPIO\_0 | 3 | - | I2S\_BCLK | I^2^S Bit Clock | | 4 | VDDIO\_1 | DI/DO | GPIO\_0 | 4 | - | - | - | | 4 | VDDIO\_1 | DI/DO | GPIO\_0 | 5 | - | I2C0\_SCL | I^2^C 0 Serial Clock | | 4 | VDDIO\_1 | DI/DO | GPIO\_0 | 6 | - | I2C1\_SCL | I^2^C 1 Serial Clock | | 4 | VDDIO\_1 | DI/DO | GPIO\_0 | 7 | uart\_sig\_0\_sel=0 | UART0\_RTS | UART 0 Request To Send | | 4 | VDDIO\_1 | DI/DO | GPIO\_0 | 7 | uart\_sig\_0\_sel=1 | UART0\_CTS | UART 0 Clear To Send | | 4 | VDDIO\_1 | DI/DO | GPIO\_0 | 7 | uart\_sig\_0\_sel=2 | UART0\_TXD | UART 0 Transmit Data | | 4 | VDDIO\_1 | DI/DO | GPIO\_0 | 7 | uart\_sig\_0\_sel=3 | UART0\_RXD | UART 0 Receive Data | | 4 | VDDIO\_1 | DI/DO | GPIO\_0 | 7 | uart\_sig\_0\_sel=4 | UART1\_RTS | UART 1 Request To Send | | 4 | VDDIO\_1 | DI/DO | GPIO\_0 | 7 | uart\_sig\_0\_sel=5 | UART1\_CTS | UART 1 Clear To Send | | 4 | VDDIO\_1 | DI/DO | GPIO\_0 | 7 | uart\_sig\_0\_sel=6 | UART1\_TXD | UART 1 Transmit Data | | 4 | VDDIO\_1 | DI/DO | GPIO\_0 | 7 | uart\_sig\_0\_sel=7 | UART1\_RXD | UART 1 Receive Data | | 4 | VDDIO\_1 | DI/DO | GPIO\_0 | 7 | uart\_sig\_0\_sel=8 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 4 | VDDIO\_1 | DI/DO | GPIO\_0 | 7 | uart\_sig\_0\_sel=9 | - | - | | 4 | VDDIO\_1 | DI/DO | GPIO\_0 | 7 | uart\_sig\_0\_sel=10 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 4 | VDDIO\_1 | DI/DO | GPIO\_0 | 7 | uart\_sig\_0\_sel=11 | ISO11898\_RXD | CAN (ISO11898) Receive Data | | 4 | VDDIO\_1 | DI/DO | GPIO\_0 | 8 | - | - | - | | 4 | VDDIO\_1 | DI/DO | GPIO\_0 | 9 | - | CAM1\_VSYNC | Camera 1 Vertical Sync | | 4 | VDDIO\_1 | DI/DO | GPIO\_0 | 10 | - | ADC\_CH9 | ADC Channel 9 | | 4 | VDDIO\_1 | DI/DO | GPIO\_0 | 11 | - | SWGPIO0 | Software GPIO 0 | | 4 | VDDIO\_1 | DI/DO | GPIO\_0 | 12 | - | - | - | | 4 | VDDIO\_1 | DI/DO | GPIO\_0 | 16 | reg\_pwm1\_io\_sel=0 | PWM0\_CH0P | PWM 0 Channel 0 Positive | | 4 | VDDIO\_1 | DI/DO | GPIO\_0 | 16 | reg\_pwm1\_io\_sel=1 | PWM0\_CH0P | PWM 0 Channel 0 Positive | | 4 | VDDIO\_1 | DI/DO | GPIO\_0 | 22 | - | - | - | | 4 | VDDIO\_1 | DI/DO | GPIO\_0 | 23 | - | - | - | | 4 | VDDIO\_1 | DI/DO | GPIO\_0 | 24 | - | - | - | | 4 | VDDIO\_1 | DI/DO | GPIO\_0 | 25 | - | - | - | | 4 | VDDIO\_1 | DI/DO | GPIO\_0 | 26 | - | M0\_JTAG\_TMS | M0 JTAG Test Mode Select | | 5 | VDDIO\_1 | DI/DO | GPIO\_1 | 0 | - | - | - | | 5 | VDDIO\_1 | DI/DO | GPIO\_1 | 1 | - | SPI\_SCLK | SPI Serial Clock | | 5 | VDDIO\_1 | DI/DO | GPIO\_1 | 2 | - | - | - | | 5 | VDDIO\_1 | DI/DO | GPIO\_1 | 3 | - | I2S\_FS | I^2^S Frame Sync | | 5 | VDDIO\_1 | DI/DO | GPIO\_1 | 4 | - | - | - | | 5 | VDDIO\_1 | DI/DO | GPIO\_1 | 5 | - | I2C0\_SDA | I^2^C 0 Serial Data | | 5 | VDDIO\_1 | DI/DO | GPIO\_1 | 6 | - | I2C1\_SDA | I^2^C 1 Serial Data | | 5 | VDDIO\_1 | DI/DO | GPIO\_1 | 7 | uart\_sig\_1\_sel=0 | UART0\_RTS | UART 0 Request To Send | | 5 | VDDIO\_1 | DI/DO | GPIO\_1 | 7 | uart\_sig\_1\_sel=1 | UART0\_CTS | UART 0 Clear To Send | | 5 | VDDIO\_1 | DI/DO | GPIO\_1 | 7 | uart\_sig\_1\_sel=2 | UART0\_TXD | UART 0 Transmit Data | | 5 | VDDIO\_1 | DI/DO | GPIO\_1 | 7 | uart\_sig\_1\_sel=3 | UART0\_RXD | UART 0 Receive Data | | 5 | VDDIO\_1 | DI/DO | GPIO\_1 | 7 | uart\_sig\_1\_sel=4 | UART1\_RTS | UART 1 Request To Send | | 5 | VDDIO\_1 | DI/DO | GPIO\_1 | 7 | uart\_sig\_1\_sel=5 | UART1\_CTS | UART 1 Clear To Send | | 5 | VDDIO\_1 | DI/DO | GPIO\_1 | 7 | uart\_sig\_1\_sel=6 | UART1\_TXD | UART 1 Transmit Data | | 5 | VDDIO\_1 | DI/DO | GPIO\_1 | 7 | uart\_sig\_1\_sel=7 | UART1\_RXD | UART 1 Receive Data | | 5 | VDDIO\_1 | DI/DO | GPIO\_1 | 7 | uart\_sig\_1\_sel=8 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 5 | VDDIO\_1 | DI/DO | GPIO\_1 | 7 | uart\_sig\_1\_sel=9 | - | - | | 5 | VDDIO\_1 | DI/DO | GPIO\_1 | 7 | uart\_sig\_1\_sel=10 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 5 | VDDIO\_1 | DI/DO | GPIO\_1 | 7 | uart\_sig\_1\_sel=11 | ISO11898\_RXD | CAN (ISO 11898) Receive Data | | 5 | VDDIO\_1 | DI/DO | GPIO\_1 | 8 | - | - | - | | 5 | VDDIO\_1 | DI/DO | GPIO\_1 | 9 | - | CAM1\_HSYNC | Camera 1 Horizontal Sync | | 5 | VDDIO\_1 | DI/DO | GPIO\_1 | 10 | - | ADC\_CH8 | ADC Channel 8 | | 5 | VDDIO\_1 | DI/DO | GPIO\_1 | 11 | - | SWGPIO1 | Software GPIO1 | | 5 | VDDIO\_1 | DI/DO | GPIO\_1 | 12 | - | - | - | | 5 | VDDIO\_1 | DI/DO | GPIO\_1 | 16 | reg\_pwm1\_io\_sel=0 | PWM0\_CH1P | PWM 0 Channel 1 Positive | | 5 | VDDIO\_1 | DI/DO | GPIO\_1 | 16 | reg\_pwm1\_io\_sel=1 | PWM0\_CH0N | PWM 0 Channel 0 Negative | | 5 | VDDIO\_1 | DI/DO | GPIO\_1 | 22 | - | - | - | | 5 | VDDIO\_1 | DI/DO | GPIO\_1 | 23 | - | - | - | | 5 | VDDIO\_1 | DI/DO | GPIO\_1 | 24 | - | - | - | | 5 | VDDIO\_1 | DI/DO | GPIO\_1 | 25 | - | - | - | | 5 | VDDIO\_1 | DI/DO | GPIO\_1 | 26 | - | M0\_JTAG\_TCK | M0 JTAG Test Clock | | 6 | VDDIO\_1 | DI/DO | GPIO\_2 | 0 | - | - | | | 6 | VDDIO\_1 | DI/DO | GPIO\_2 | 1 | - | SPI\_MISO | SPI Master Input, Slave Output | | 6 | VDDIO\_1 | DI/DO | GPIO\_2 | 2 | - | - | - | | 6 | VDDIO\_1 | DI/DO | GPIO\_2 | 3 | - | I2S\_DI/I2S\_RCLK\_O | I^2^S Data Input/I^2^S Receive Clock Output | | 6 | VDDIO\_1 | DI/DO | GPIO\_2 | 4 | - | - | - | | 6 | VDDIO\_1 | DI/DO | GPIO\_2 | 5 | - | I2C0\_SCL | I^2^C 0 Serial Clock | | 6 | VDDIO\_1 | DI/DO | GPIO\_2 | 6 | - | I2C1\_SCL | I^2^C 1 Serial Clock | | 6 | VDDIO\_1 | DI/DO | GPIO\_2 | 7 | uart\_sig\_2\_sel=0 | UART0\_RTS | UART 0 Request To Send | | 6 | VDDIO\_1 | DI/DO | GPIO\_2 | 7 | uart\_sig\_2\_sel=1 | UART0\_CTS | UART 0 Clear To Send | | 6 | VDDIO\_1 | DI/DO | GPIO\_2 | 7 | uart\_sig\_2\_sel=2 | UART0\_TXD | UART 0 Transmit Data | | 6 | VDDIO\_1 | DI/DO | GPIO\_2 | 7 | uart\_sig\_2\_sel=3 | UART0\_RXD | UART 0 Receive Data | | 6 | VDDIO\_1 | DI/DO | GPIO\_2 | 7 | uart\_sig\_2\_sel=4 | UART1\_RTS | UART 1 Request To Send | | 6 | VDDIO\_1 | DI/DO | GPIO\_2 | 7 | uart\_sig\_2\_sel=5 | UART1\_CTS | UART 1 Clear To Send | | 6 | VDDIO\_1 | DI/DO | GPIO\_2 | 7 | uart\_sig\_2\_sel=6 | UART1\_TXD | UART 1 Transmit Data | | 6 | VDDIO\_1 | DI/DO | GPIO\_2 | 7 | uart\_sig\_2\_sel=7 | UART1\_RXD | UART 1 Receive Data | | 6 | VDDIO\_1 | DI/DO | GPIO\_2 | 7 | uart\_sig\_2\_sel=8 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 6 | VDDIO\_1 | DI/DO | GPIO\_2 | 7 | uart\_sig\_2\_sel=9 | - | - | | 6 | VDDIO\_1 | DI/DO | GPIO\_2 | 7 | uart\_sig\_2\_sel=10 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 6 | VDDIO\_1 | DI/DO | GPIO\_2 | 7 | uart\_sig\_2\_sel=11 | ISO11898\_RXD | CAN (ISO 11898) Receive Data | | 6 | VDDIO\_1 | DI/DO | GPIO\_2 | 8 | - | - | - | | 6 | VDDIO\_1 | DI/DO | GPIO\_2 | 9 | - | - | - | | 6 | VDDIO\_1 | DI/DO | GPIO\_2 | 10 | - | ADC\_CH2 | ADC Channel 2 | | 6 | VDDIO\_1 | DI/DO | GPIO\_2 | 11 | - | SWGPIO2 | Software GPIO 2 | | 6 | VDDIO\_1 | DI/DO | GPIO\_2 | 12 | - | - | - | | 6 | VDDIO\_1 | DI/DO | GPIO\_2 | 16 | reg\_pwm1\_io\_sel=0 | PWM0\_CH2P | PWM 0 Channel 2 Positive | | 6 | VDDIO\_1 | DI/DO | GPIO\_2 | 16 | reg\_pwm1\_io\_sel=1 | PWM0\_CH1P | PWM 0 Channel 1 Positive | | 6 | VDDIO\_1 | DI/DO | GPIO\_2 | 22 | - | - | - | | 6 | VDDIO\_1 | DI/DO | GPIO\_2 | 23 | - | - | - | | 6 | VDDIO\_1 | DI/DO | GPIO\_2 | 24 | - | - | - | | 6 | VDDIO\_1 | DI/DO | GPIO\_2 | 25 | - | - | - | | 6 | VDDIO\_1 | DI/DO | GPIO\_2 | 26 | - | M0\_JTAG\_TDO | M0 JTAG Test Data Out | | 7 | VDDIO\_1 | DI/DO | GPIO\_3 | 0 | - | - | - | | 7 | VDDIO\_1 | DI/DO | GPIO\_3 | 1 | - | SPI\_MOSI | SPI Master Output, Slave Input | | 7 | VDDIO\_1 | DI/DO | GPIO\_3 | 2 | - | - | - | | 7 | VDDIO\_1 | DI/DO | GPIO\_3 | 3 | - | I2S\_DO/I2S\_RCLK\_O | I^2^S Data Output/I^2^S Receive Clock
Output | | 7 | VDDIO\_1 | DI/DO | GPIO\_3 | 4 | - | - | - | | 7 | VDDIO\_1 | DI/DO | GPIO\_3 | 5 | - | I2C0\_SDA | I^2^C 0 Serial Data | | 7 | VDDIO\_1 | DI/DO | GPIO\_3 | 6 | - | I2C1\_SDA | I^2^C 1 Serial Data | | 7 | VDDIO\_1 | DI/DO | GPIO\_3 | 7 | uart\_sig\_3\_sel=0 | UART0\_RTS | UART 0 Request To Send | | 7 | VDDIO\_1 | DI/DO | GPIO\_3 | 7 | uart\_sig\_3\_sel=1 | UART0\_CTS | UART 0 Clear To Send | | 7 | VDDIO\_1 | DI/DO | GPIO\_3 | 7 | uart\_sig\_3\_sel=2 | UART0\_TXD | UART 0 Transmit Data | | 7 | VDDIO\_1 | DI/DO | GPIO\_3 | 7 | uart\_sig\_3\_sel=3 | UART0\_RXD | UART 0 Receive Data | | 7 | VDDIO\_1 | DI/DO | GPIO\_3 | 7 | uart\_sig\_3\_sel=4 | UART1\_RTS | UART 1 Request To Send | | 7 | VDDIO\_1 | DI/DO | GPIO\_3 | 7 | uart\_sig\_3\_sel=5 | UART1\_CTS | UART 1 Clear To Send | | 7 | VDDIO\_1 | DI/DO | GPIO\_3 | 7 | uart\_sig\_3\_sel=6 | UART1\_TXD | UART 1 Transmit Data | | 7 | VDDIO\_1 | DI/DO | GPIO\_3 | 7 | uart\_sig\_3\_sel=7 | UART1\_RXD | UART 1 Receive Data | | 7 | VDDIO\_1 | DI/DO | GPIO\_3 | 7 | uart\_sig\_3\_sel=8 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 7 | VDDIO\_1 | DI/DO | GPIO\_3 | 7 | uart\_sig\_3\_sel=9 | - | - | | 7 | VDDIO\_1 | DI/DO | GPIO\_3 | 7 | uart\_sig\_3\_sel=10 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 7 | VDDIO\_1 | DI/DO | GPIO\_3 | 7 | uart\_sig\_3\_sel=11 | ISO11898\_RXD | CAN (ISO 11898) Receive Data | | 7 | VDDIO\_1 | DI/DO | GPIO\_3 | 8 | - | - | - | | 7 | VDDIO\_1 | DI/DO | GPIO\_3 | 9 | - | CAM1\_DAT0 | Camera 1 Data 0 | | 7 | VDDIO\_1 | DI/DO | GPIO\_3 | 10 | - | ADC\_CH3 | ADC Channel 3 | | 7 | VDDIO\_1 | DI/DO | GPIO\_3 | 11 | - | SWGPIO3 | Software GPIO 3 | | 7 | VDDIO\_1 | DI/DO | GPIO\_3 | 12 | - | - | - | | 7 | VDDIO\_1 | DI/DO | GPIO\_3 | 16 | reg\_pwm1\_io\_sel=0 | PWM0\_CH3P | PWM 0 Channel 3 Positive | | 7 | VDDIO\_1 | DI/DO | GPIO\_3 | 16 | reg\_pwm1\_io\_sel=1 | PWM0\_CH1N | PWM 0 Channel 1 Negative | | 7 | VDDIO\_1 | DI/DO | GPIO\_3 | 22 | - | - | - | | 7 | VDDIO\_1 | DI/DO | GPIO\_3 | 23 | - | - | - | | 7 | VDDIO\_1 | DI/DO | GPIO\_3 | 24 | - | - | - | | 7 | VDDIO\_1 | DI/DO | GPIO\_3 | 25 | - | - | - | | 7 | VDDIO\_1 | DI/DO | GPIO\_3 | 26 | - | M0\_JTAG\_TDI | M0 JTAG Test Data Input | | 8 | VDDIO\_1 | DI/DO | GPIO\_4 | 0 | - | - | - | | 8 | VDDIO\_1 | DI/DO | GPIO\_4 | 1 | - | SPI\_SS | SPI Slave Select | | 8 | VDDIO\_1 | DI/DO | GPIO\_4 | 2 | - | SF2\_CS | SF2 Chip Select | | 8 | VDDIO\_1 | DI/DO | GPIO\_4 | 3 | - | I2S\_BCLK | I^2^S Bit Clock | | 8 | VDDIO\_1 | DI/DO | GPIO\_4 | 4 | - | - | - | | 8 | VDDIO\_1 | DI/DO | GPIO\_4 | 5 | - | I2C0\_SCL | I^2^C 0 Serial Clock | | 8 | VDDIO\_1 | DI/DO | GPIO\_4 | 6 | - | I2C1\_SCL | I^2^C 1 Serial Clock | | 8 | VDDIO\_1 | DI/DO | GPIO\_4 | 7 | uart\_sig\_4\_sel=0 | UART0\_RTS | UART 0 Request To Send | | 8 | VDDIO\_1 | DI/DO | GPIO\_4 | 7 | uart\_sig\_4\_sel=1 | UART0\_CTS | UART 0 Clear To Send | | 8 | VDDIO\_1 | DI/DO | GPIO\_4 | 7 | uart\_sig\_4\_sel=2 | UART0\_TXD | UART 0 Transmit Data | | 8 | VDDIO\_1 | DI/DO | GPIO\_4 | 7 | uart\_sig\_4\_sel=3 | UART0\_RXD | UART 0 Receive Data | | 8 | VDDIO\_1 | DI/DO | GPIO\_4 | 7 | uart\_sig\_4\_sel=4 | UART1\_RTS | UART 1 Request To Send | | 8 | VDDIO\_1 | DI/DO | GPIO\_4 | 7 | uart\_sig\_4\_sel=5 | UART1\_CTS | UART 1 Clear To Send | | 8 | VDDIO\_1 | DI/DO | GPIO\_4 | 7 | uart\_sig\_4\_sel=6 | UART1\_TXD | UART 1 Transmit Data | | 8 | VDDIO\_1 | DI/DO | GPIO\_4 | 7 | uart\_sig\_4\_sel=7 | UART1\_RXD | UART 1 Receive Data | | 8 | VDDIO\_1 | DI/DO | GPIO\_4 | 7 | uart\_sig\_4\_sel=8 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 8 | VDDIO\_1 | DI/DO | GPIO\_4 | 7 | uart\_sig\_4\_sel=9 | - | - | | 8 | VDDIO\_1 | DI/DO | GPIO\_4 | 7 | uart\_sig\_4\_sel=10 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 8 | VDDIO\_1 | DI/DO | GPIO\_4 | 7 | uart\_sig\_4\_sel=11 | ISO11898\_RXD | CAN (ISO 11898) Receive Data | | 8 | VDDIO\_1 | DI/DO | GPIO\_4 | 8 | - | - | - | | 8 | VDDIO\_1 | DI/DO | GPIO\_4 | 9 | - | - | - | | 8 | VDDIO\_1 | DI/DO | GPIO\_4 | 10 | - | - | - | | 8 | VDDIO\_1 | DI/DO | GPIO\_4 | 11 | - | SWGPIO4 | Software GPIO 4 | | 8 | VDDIO\_1 | DI/DO | GPIO\_4 | 12 | - | - | - | | 8 | VDDIO\_1 | DI/DO | GPIO\_4 | 16 | reg\_pwm1\_io\_sel=0 | PWM0\_CH0P | PWM 0 Channel 0 Positive | | 8 | VDDIO\_1 | DI/DO | GPIO\_4 | 16 | reg\_pwm1\_io\_sel=1 | PWM0\_CH2P | PWM 0 Channel 2 Positive | | 8 | VDDIO\_1 | DI/DO | GPIO\_4 | 22 | - | DBI\_TypeB\_WRn | Display Bus Interface Type B Write Control | | 8 | VDDIO\_1 | DI/DO | GPIO\_4 | 23 | - | DBI\_TypeC\_SCL | Display Bus Interface Type C Serial Clock | | 8 | VDDIO\_1 | DI/DO | GPIO\_4 | 24 | - | DISP\_QSPI\_SCL | Display Quad SPI Serial Clock | | 8 | VDDIO\_1 | DI/DO | GPIO\_4 | 25 | - | - | - | | 8 | VDDIO\_1 | DI/DO | GPIO\_4 | 26 | - | M0\_JTAG\_TMS | M0 JTAG Test Mode Select | | 9 | VDDIO\_1 | DI/DO | GPIO\_5 | 0 | - | - | - | | 9 | VDDIO\_1 | DI/DO | GPIO\_5 | 1 | - | SPI\_SCLK | SPI Serial Clock | | 9 | VDDIO\_1 | DI/DO | GPIO\_5 | 2 | - | SF2\_D1 | SF2 Data 1 | | 9 | VDDIO\_1 | DI/DO | GPIO\_5 | 3 | - | I2S\_FS | I^2^S Frame Sync | | 9 | VDDIO\_1 | DI/DO | GPIO\_5 | 4 | - | - | - | | 9 | VDDIO\_1 | DI/DO | GPIO\_5 | 5 | - | I2C0\_SDA | I^2^C 0 Serial Data | | 9 | VDDIO\_1 | DI/DO | GPIO\_5 | 6 | - | I2C1\_SDA | I^2^C 1 Serial Data | | 9 | VDDIO\_1 | DI/DO | GPIO\_5 | 7 | uart\_sig\_5\_sel=0 | UART0\_RTS | UART 0 Request To Send | | 9 | VDDIO\_1 | DI/DO | GPIO\_5 | 7 | uart\_sig\_5\_sel=1 | UART0\_CTS | UART 0 Clear To Send | | 9 | VDDIO\_1 | DI/DO | GPIO\_5 | 7 | uart\_sig\_5\_sel=2 | UART0\_TXD | UART 0 Transmit Data | | 9 | VDDIO\_1 | DI/DO | GPIO\_5 | 7 | uart\_sig\_5\_sel=3 | UART0\_RXD | UART 0 Receive Data | | 9 | VDDIO\_1 | DI/DO | GPIO\_5 | 7 | uart\_sig\_5\_sel=4 | UART1\_RTS | UART 1 Request To Send | | 9 | VDDIO\_1 | DI/DO | GPIO\_5 | 7 | uart\_sig\_5\_sel=5 | UART1\_CTS | UART 1 Clear To Send | | 9 | VDDIO\_1 | DI/DO | GPIO\_5 | 7 | uart\_sig\_5\_sel=6 | UART1\_TXD | UART 1 Transmit Data | | 9 | VDDIO\_1 | DI/DO | GPIO\_5 | 7 | uart\_sig\_5\_sel=7 | UART1\_RXD | UART 1 Receive Data | | 9 | VDDIO\_1 | DI/DO | GPIO\_5 | 7 | uart\_sig\_5\_sel=8 | ISO11898\_TXD | CAN (ISO11898) Transmit Data | | 9 | VDDIO\_1 | DI/DO | GPIO\_5 | 7 | uart\_sig\_5\_sel=9 | - | - | | 9 | VDDIO\_1 | DI/DO | GPIO\_5 | 7 | uart\_sig\_5\_sel=10 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 9 | VDDIO\_1 | DI/DO | GPIO\_5 | 7 | uart\_sig\_5\_sel=11 | ISO11898\_RXD | CAN (ISO 11898) Receive Data | | 9 | VDDIO\_1 | DI/DO | GPIO\_5 | 8 | - | - | - | | 9 | VDDIO\_1 | DI/DO | GPIO\_5 | 9 | - | - | - | | 9 | VDDIO\_1 | DI/DO | GPIO\_5 | 10 | - | - | - | | 9 | VDDIO\_1 | DI/DO | GPIO\_5 | 11 | - | SWGPIO5 | Software GPIO 5 | | 9 | VDDIO\_1 | DI/DO | GPIO\_5 | 12 | - | - | - | | 9 | VDDIO\_1 | DI/DO | GPIO\_5 | 16 | reg\_pwm1\_io\_sel=0 | PWM0\_CH1P | PWM 0 Channel 1 Positive | | 9 | VDDIO\_1 | DI/DO | GPIO\_5 | 16 | reg\_pwm1\_io\_sel=1 | PWM0\_CH2N | PWM 0 Channel 2 Negative | | 9 | VDDIO\_1 | DI/DO | GPIO\_5 | 22 | - | DBI\_TypeB\_CSn | Display Bus Interface Type B Chip Select | | 9 | VDDIO\_1 | DI/DO | GPIO\_5 | 23 | - | DBI\_TypeC\_CSn | Display Bus Interface Type C Chip Select | | 9 | VDDIO\_1 | DI/DO | GPIO\_5 | 24 | - | DISP\_QSPI\_CSn | Display Quad SPI Chip Select | | 9 | VDDIO\_1 | DI/DO | GPIO\_5 | 25 | - | - | - | | 9 | VDDIO\_1 | DI/DO | GPIO\_5 | 26 | - | M0\_JTAG\_TCK | M0 JTAG Test Clock | | 10 | VDDIO\_1 | DI/DO | GPIO\_6 | 0 | - | - | - | | 10 | VDDIO\_1 | DI/DO | GPIO\_6 | 1 | - | SPI\_MISO | SPI Master Input, Slave Output | | 10 | VDDIO\_1 | DI/DO | GPIO\_6 | 2 | - | SF2\_D2 | SF2 Data 2 | | 10 | VDDIO\_1 | DI/DO | GPIO\_6 | 3 | - | I2S\_DI/I2S\_RCLK\_O | I^2^S Data Input/I^2^S Receive Clock Output | | 10 | VDDIO\_1 | DI/DO | GPIO\_6 | 4 | - | - | - | | 10 | VDDIO\_1 | DI/DO | GPIO\_6 | 5 | - | I2C0\_SCL | I^2^C 0 Serial Clock | | 10 | VDDIO\_1 | DI/DO | GPIO\_6 | 6 | - | I2C1\_SCL | I^2^C 1 Serial Clock | | 10 | VDDIO\_1 | DI/DO | GPIO\_6 | 7 | uart\_sig\_6\_sel=0 | UART0\_RTS | UART 0 Request To Send | | 10 | VDDIO\_1 | DI/DO | GPIO\_6 | 7 | uart\_sig\_6\_sel=1 | UART0\_CTS | UART 0 Clear To Send | | 10 | VDDIO\_1 | DI/DO | GPIO\_6 | 7 | uart\_sig\_6\_sel=2 | UART0\_TXD | UART 0 Transmit Data | | 10 | VDDIO\_1 | DI/DO | GPIO\_6 | 7 | uart\_sig\_6\_sel=3 | UART0\_RXD | UART 0 Receive Data | | 10 | VDDIO\_1 | DI/DO | GPIO\_6 | 7 | uart\_sig\_6\_sel=4 | UART1\_RTS | UART 1 Request To Send | | 10 | VDDIO\_1 | DI/DO | GPIO\_6 | 7 | uart\_sig\_6\_sel=5 | UART1\_CTS | UART 1 Clear To Send | | 10 | VDDIO\_1 | DI/DO | GPIO\_6 | 7 | uart\_sig\_6\_sel=6 | UART1\_TXD | UART 1 Transmit Data | | 10 | VDDIO\_1 | DI/DO | GPIO\_6 | 7 | uart\_sig\_6\_sel=7 | UART1\_RXD | UART 1 Receive Data | | 10 | VDDIO\_1 | DI/DO | GPIO\_6 | 7 | uart\_sig\_6\_sel=8 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 10 | VDDIO\_1 | DI/DO | GPIO\_6 | 7 | uart\_sig\_6\_sel=9 | - | - | | 10 | VDDIO\_1 | DI/DO | GPIO\_6 | 7 | uart\_sig\_6\_sel=10 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 10 | VDDIO\_1 | DI/DO | GPIO\_6 | 7 | uart\_sig\_6\_sel=11 | ISO11898\_RXD | CAN (ISO 11898) Receive Data | | 10 | VDDIO\_1 | DI/DO | GPIO\_6 | 8 | - | - | - | | 10 | VDDIO\_1 | DI/DO | GPIO\_6 | 9 | - | - | - | | 10 | VDDIO\_1 | DI/DO | GPIO\_6 | 10 | - | - | - | | 10 | VDDIO\_1 | DI/DO | GPIO\_6 | 11 | - | SWGPIO6 | Software GPIO 6 | | 10 | VDDIO\_1 | DI/DO | GPIO\_6 | 12 | - | - | - | | 10 | VDDIO\_1 | DI/DO | GPIO\_6 | 16 | reg\_pwm1\_io\_sel=0 | PWM0\_CH2P | PWM 0 Channel 2 Positive | | 10 | VDDIO\_1 | DI/DO | GPIO\_6 | 16 | reg\_pwm1\_io\_sel=1 | PWM0\_CH3P | PWM 0 Channel 3 Positive | | 10 | VDDIO\_1 | DI/DO | GPIO\_6 | 22 | - | DBI\_TypeB\_RDn | Display Bus Interface Type B Read Control | | 10 | VDDIO\_1 | DI/DO | GPIO\_6 | 23 | - | DBI\_TypeC\_SDA0 | Display Bus Interface Type C Serial Data 0 | | 10 | VDDIO\_1 | DI/DO | GPIO\_6 | 24 | - | DISP\_QSPI\_SDA0 | Display Quad SPI Serial Data 0 | | 10 | VDDIO\_1 | DI/DO | GPIO\_6 | 25 | - | - | | | 10 | VDDIO\_1 | DI/DO | GPIO\_6 | 26 | - | M0\_JTAG\_TDO | M0 JTAG Test Data Out | | 11 | VDDIO\_1 | DI/DO | GPIO\_7 | 0 | - | - | - | | 11 | VDDIO\_1 | DI/DO | GPIO\_7 | 1 | - | SPI\_MOSI | SPI Master Output, Slave Input | | 11 | VDDIO\_1 | DI/DO | GPIO\_7 | 2 | - | SF2\_D0 | SF2 Data 0 | | 11 | VDDIO\_1 | DI/DO | GPIO\_7 | 3 | - | I2S\_DO/I2S\_RCLK\_O | I^2^S Data Output/I^2^S Receive Clock
Output | | 11 | VDDIO\_1 | DI/DO | GPIO\_7 | 4 | - | - | - | | 11 | VDDIO\_1 | DI/DO | GPIO\_7 | 5 | - | I2C0\_SDA | I^2^C 0 Serial Data | | 11 | VDDIO\_1 | DI/DO | GPIO\_7 | 6 | - | I2C1\_SDA | I^2^C 1 Serial Data | | 11 | VDDIO\_1 | DI/DO | GPIO\_7 | 7 | uart\_sig\_7\_sel=0 | UART0\_RTS | UART 0 Request To Send | | 11 | VDDIO\_1 | DI/DO | GPIO\_7 | 7 | uart\_sig\_7\_sel=1 | UART0\_CTS | UART 0 Clear To Send | | 11 | VDDIO\_1 | DI/DO | GPIO\_7 | 7 | uart\_sig\_7\_sel=2 | UART0\_TXD | UART 0 Transmit Data | | 11 | VDDIO\_1 | DI/DO | GPIO\_7 | 7 | uart\_sig\_7\_sel=3 | UART0\_RXD | UART 0 Receive Data | | 11 | VDDIO\_1 | DI/DO | GPIO\_7 | 7 | uart\_sig\_7\_sel=4 | UART1\_RTS | UART 1 Request To Send | | 11 | VDDIO\_1 | DI/DO | GPIO\_7 | 7 | uart\_sig\_7\_sel=5 | UART1\_CTS | UART 1 Clear To Send | | 11 | VDDIO\_1 | DI/DO | GPIO\_7 | 7 | uart\_sig\_7\_sel=6 | UART1\_TXD | UART 1 Transmit Data | | 11 | VDDIO\_1 | DI/DO | GPIO\_7 | 7 | uart\_sig\_7\_sel=7 | UART1\_RXD | UART 1 Receive Data | | 11 | VDDIO\_1 | DI/DO | GPIO\_7 | 7 | uart\_sig\_7\_sel=8 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 11 | VDDIO\_1 | DI/DO | GPIO\_7 | 7 | uart\_sig\_7\_sel=9 | - | - | | 11 | VDDIO\_1 | DI/DO | GPIO\_7 | 7 | uart\_sig\_7\_sel=10 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 11 | VDDIO\_1 | DI/DO | GPIO\_7 | 7 | uart\_sig\_7\_sel=11 | ISO11898\_RXD | CAN (ISO 11898) Receive Data | | 11 | VDDIO\_1 | DI/DO | GPIO\_7 | 8 | - | - | - | | 11 | VDDIO\_1 | DI/DO | GPIO\_7 | 9 | - | - | - | | 11 | VDDIO\_1 | DI/DO | GPIO\_7 | 10 | - | - | - | | 11 | VDDIO\_1 | DI/DO | GPIO\_7 | 11 | - | SWGPIO7 | Software GPIO 7 | | 11 | VDDIO\_1 | DI/DO | GPIO\_7 | 12 | - | - | - | | 11 | VDDIO\_1 | DI/DO | GPIO\_7 | 16 | reg\_pwm1\_io\_sel=0 | PWM0\_CH3P | PWM 0 Channel 3 Positive | | 11 | VDDIO\_1 | DI/DO | GPIO\_7 | 16 | reg\_pwm1\_io\_sel=1 | PWM0\_CH3N | PWM 0 Channel 3 Negative | | 11 | VDDIO\_1 | DI/DO | GPIO\_7 | 22 | - | DBI\_TypeB\_DCn | Display Bus Interface Type B Data/Command Control | | 11 | VDDIO\_1 | DI/DO | GPIO\_7 | 23 | - | DBI\_TypeC\_DCn | Display Bus Interface Type C Data/Command Control | | 11 | VDDIO\_1 | DI/DO | GPIO\_7 | 24 | - | DISP\_QSPI\_SDA1 | Display Quad SPI Serial Data 1 | | 11 | VDDIO\_1 | DI/DO | GPIO\_7 | 25 | - | - | - | | 11 | VDDIO\_1 | DI/DO | GPIO\_7 | 26 | - | M0\_JTAG\_TDI | M0 JTAG Test Data Input | | 12 | VDDIO\_1 | DI/DO | GPIO\_8 | 0 | - | - | - | | 12 | VDDIO\_1 | DI/DO | GPIO\_8 | 1 | - | SPI\_SS | SPI Slave Select | | 12 | VDDIO\_1 | DI/DO | GPIO\_8 | 2 | - | SF2\_CLK | SF2 Clock | | 12 | VDDIO\_1 | DI/DO | GPIO\_8 | 3 | - | I2S\_BCLK | I^2^S Bit Clock | | 12 | VDDIO\_1 | DI/DO | GPIO\_8 | 4 | - | - | - | | 12 | VDDIO\_1 | DI/DO | GPIO\_8 | 5 | - | I2C0\_SCL | I^2^C 0 Serial Clock | | 12 | VDDIO\_1 | DI/DO | GPIO\_8 | 6 | - | I2C1\_SCL | I^2^C 1 Serial Clock | | 12 | VDDIO\_1 | DI/DO | GPIO\_8 | 7 | uart\_sig\_8\_sel=0 | UART0\_RTS | UART 0 Request To Send | | 12 | VDDIO\_1 | DI/DO | GPIO\_8 | 7 | uart\_sig\_8\_sel=1 | UART0\_CTS | UART 0 Clear To Send | | 12 | VDDIO\_1 | DI/DO | GPIO\_8 | 7 | uart\_sig\_8\_sel=2 | UART0\_TXD | UART 0 Transmit Data | | 12 | VDDIO\_1 | DI/DO | GPIO\_8 | 7 | uart\_sig\_8\_sel=3 | UART0\_RXD | UART 0 Receive Data | | 12 | VDDIO\_1 | DI/DO | GPIO\_8 | 7 | uart\_sig\_8\_sel=4 | UART1\_RTS | UART 1 Request To Send | | 12 | VDDIO\_1 | DI/DO | GPIO\_8 | 7 | uart\_sig\_8\_sel=5 | UART1\_CTS | UART 1 Clear To Send | | 12 | VDDIO\_1 | DI/DO | GPIO\_8 | 7 | uart\_sig\_8\_sel=6 | UART1\_TXD | UART 1 Transmit Data | | 12 | VDDIO\_1 | DI/DO | GPIO\_8 | 7 | uart\_sig\_8\_sel=7 | UART1\_RXD | UART 1 Receive Data | | 12 | VDDIO\_1 | DI/DO | GPIO\_8 | 7 | uart\_sig\_8\_sel=8 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 12 | VDDIO\_1 | DI/DO | GPIO\_8 | 7 | uart\_sig\_8\_sel=9 | - | - | | 12 | VDDIO\_1 | DI/DO | GPIO\_8 | 7 | uart\_sig\_8\_sel=10 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 12 | VDDIO\_1 | DI/DO | GPIO\_8 | 7 | uart\_sig\_8\_sel=11 | ISO11898\_RXD | CAN (ISO 11898) Receive Data | | 12 | VDDIO\_1 | DI/DO | GPIO\_8 | 8 | - | - | - | | 12 | VDDIO\_1 | DI/DO | GPIO\_8 | 9 | - | - | - | | 12 | VDDIO\_1 | DI/DO | GPIO\_8 | 10 | - | - | - | | 12 | VDDIO\_1 | DI/DO | GPIO\_8 | 11 | - | SWGPIO8 | Software GPIO 8 | | 12 | VDDIO\_1 | DI/DO | GPIO\_8 | 12 | - | - | - | | 12 | VDDIO\_1 | DI/DO | GPIO\_8 | 16 | reg\_pwm1\_io\_sel=0 | PWM0\_CH0P | PWM 0 Channel 0 Positive | | 12 | VDDIO\_1 | DI/DO | GPIO\_8 | 16 | reg\_pwm1\_io\_sel=1 | PWM0\_CH0P | PWM 0 Channel 0 Positive | | 12 | VDDIO\_1 | DI/DO | GPIO\_8 | 22 | - | DBI\_TypeB\_DB0 | Display Bus Interface Type B Data Bit 0 | | 12 | VDDIO\_1 | DI/DO | GPIO\_8 | 23 | - | DBI\_TypeC\_SCL | Display Bus Interface Type C Serial Clock | | 12 | VDDIO\_1 | DI/DO | GPIO\_8 | 24 | - | DISP\_QSPI\_SDA2 | Display Quad SPI Serial Data 2 | | 12 | VDDIO\_1 | DI/DO | GPIO\_8 | 25 | - | - | - | | 12 | VDDIO\_1 | DI/DO | GPIO\_8 | 26 | - | M0\_JTAG\_TMS | M0 JTAG Test Mode Select | | 13 | - | Power, Input | VDDIO1 | - | - | VDDIO1 | 1.8 V/3.3 V power supply of GPIO0 to GPIO19 | | 14 | VDDIO\_1 | DI/DO | GPIO\_9 | 0 | - | - | - | | 14 | VDDIO\_1 | DI/DO | GPIO\_9 | 1 | - | SPI\_SCLK | SPI Serial Clock | | 14 | VDDIO\_1 | DI/DO | GPIO\_9 | 2 | - | SF2\_D3 | SF2 Data 3 | | 14 | VDDIO\_1 | DI/DO | GPIO\_9 | 3 | - | I2S\_FS | I^2^S Frame Sync | | 14 | VDDIO\_1 | DI/DO | GPIO\_9 | 4 | - | - | - | | 14 | VDDIO\_1 | DI/DO | GPIO\_9 | 5 | - | I2C0\_SDA | I^2^C 0 Serial Data | | 14 | VDDIO\_1 | DI/DO | GPIO\_9 | 6 | - | I2C1\_SDA | I^2^C 1 Serial Data | | 14 | VDDIO\_1 | DI/DO | GPIO\_9 | 7 | uart\_sig\_9\_sel=0 | UART0\_RTS | UART 0 Request To Send | | 14 | VDDIO\_1 | DI/DO | GPIO\_9 | 7 | uart\_sig\_9\_sel=1 | UART0\_CTS | UART 0 Clear To Send | | 14 | VDDIO\_1 | DI/DO | GPIO\_9 | 7 | uart\_sig\_9\_sel=2 | UART0\_TXD | UART 0 Transmit Data | | 14 | VDDIO\_1 | DI/DO | GPIO\_9 | 7 | uart\_sig\_9\_sel=3 | UART0\_RXD | UART 0 Receive Data | | 14 | VDDIO\_1 | DI/DO | GPIO\_9 | 7 | uart\_sig\_9\_sel=4 | UART1\_RTS | UART 1 Request To Send | | 14 | VDDIO\_1 | DI/DO | GPIO\_9 | 7 | uart\_sig\_9\_sel=5 | UART1\_CTS | UART 1 Clear To Send | | 14 | VDDIO\_1 | DI/DO | GPIO\_9 | 7 | uart\_sig\_9\_sel=6 | UART1\_TXD | UART 1 Transmit Data | | 14 | VDDIO\_1 | DI/DO | GPIO\_9 | 7 | uart\_sig\_9\_sel=7 | UART1\_RXD | UART 1 Receive Data | | 14 | VDDIO\_1 | DI/DO | GPIO\_9 | 7 | uart\_sig\_9\_sel=8 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 14 | VDDIO\_1 | DI/DO | GPIO\_9 | 7 | uart\_sig\_9\_sel=9 | - | - | | 14 | VDDIO\_1 | DI/DO | GPIO\_9 | 7 | uart\_sig\_9\_sel=10 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 14 | VDDIO\_1 | DI/DO | GPIO\_9 | 7 | uart\_sig\_9\_sel=11 | ISO11898\_RXD | CAN (ISO 11898) Receive Data | | 14 | VDDIO\_1 | DI/DO | GPIO\_9 | 8 | - | - | - | | 14 | VDDIO\_1 | DI/DO | GPIO\_9 | 9 | - | - | - | | 14 | VDDIO\_1 | DI/DO | GPIO\_9 | 10 | - | - | - | | 14 | VDDIO\_1 | DI/DO | GPIO\_9 | 11 | - | SWGPIO9 | Software GPIO 9 | | 14 | VDDIO\_1 | DI/DO | GPIO\_9 | 12 | - | - | - | | 14 | VDDIO\_1 | DI/DO | GPIO\_9 | 16 | reg\_pwm1\_io\_sel=0 | PWM0\_CH1P | PWM 0 Channel 1 Positive | | 14 | VDDIO\_1 | DI/DO | GPIO\_9 | 16 | reg\_pwm1\_io\_sel=1 | PWM0\_CH0N | PWM 0 Channel 0 Negative | | 14 | VDDIO\_1 | DI/DO | GPIO\_9 | 22 | - | DBI\_TypeB\_DB1 | Display Bus Interface Type B Data Bit 1 | | 14 | VDDIO\_1 | DI/DO | GPIO\_9 | 23 | - | DBI\_TypeC\_CSn | Display Bus Interface Type C Chip Select | | 14 | VDDIO\_1 | DI/DO | GPIO\_9 | 24 | - | DISP\_QSPI\_SDA3 | Display Quad SPI Serial Data 3 | | 14 | VDDIO\_1 | DI/DO | GPIO\_9 | 25 | - | - | - | | 14 | VDDIO\_1 | DI/DO | GPIO\_9 | 26 | - | M0\_JTAG\_TCK | M0 JTAG Test Clock | | 15 | VDDIO\_1 | DI/DO | GPIO\_10 | 0 | - | SDH\_DAT1 | SD Host Data 1 | | 15 | VDDIO\_1 | DI/DO | GPIO\_10 | 1 | - | SPI\_MISO | SPI Master Input, Slave Output | | 15 | VDDIO\_1 | DI/DO | GPIO\_10 | 2 | - | SF3\_D3 | SF3 Data 3 | | 15 | VDDIO\_1 | DI/DO | GPIO\_10 | 3 | - | I2S\_DI/I2S\_RCLK\_O | I^2^S Data Input/I^2^S Receive Clock Output | | 15 | VDDIO\_1 | DI/DO | GPIO\_10 | 4 | - | - | - | | 15 | VDDIO\_1 | DI/DO | GPIO\_10 | 5 | - | I2C0\_SCL | I^2^C 0 Serial Clock | | 15 | VDDIO\_1 | DI/DO | GPIO\_10 | 6 | - | I2C1\_SCL | I^2^C 1 Serial Clock | | 15 | VDDIO\_1 | DI/DO | GPIO\_10 | 7 | uart\_sig\_10\_sel=0 | UART0\_RTS | UART 0 Request To Send | | 15 | VDDIO\_1 | DI/DO | GPIO\_10 | 7 | uart\_sig\_10\_sel=1 | UART0\_CTS | UART 0 Clear To Send | | 15 | VDDIO\_1 | DI/DO | GPIO\_10 | 7 | uart\_sig\_10\_sel=2 | UART0\_TXD | UART 0 Transmit Data | | 15 | VDDIO\_1 | DI/DO | GPIO\_10 | 7 | uart\_sig\_10\_sel=3 | UART0\_RXD | UART 0 Receive Data | | 15 | VDDIO\_1 | DI/DO | GPIO\_10 | 7 | uart\_sig\_10\_sel=4 | UART1\_RTS | UART 1 Request To Send | | 15 | VDDIO\_1 | DI/DO | GPIO\_10 | 7 | uart\_sig\_10\_sel=5 | UART1\_CTS | UART 1 Clear To Send | | 15 | VDDIO\_1 | DI/DO | GPIO\_10 | 7 | uart\_sig\_10\_sel=6 | UART1\_TXD | UART 1 Transmit Data | | 15 | VDDIO\_1 | DI/DO | GPIO\_10 | 7 | uart\_sig\_10\_sel=7 | UART1\_RXD | UART 1 Receive Data | | 15 | VDDIO\_1 | DI/DO | GPIO\_10 | 7 | uart\_sig\_10\_sel=8 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 15 | VDDIO\_1 | DI/DO | GPIO\_10 | 7 | uart\_sig\_10\_sel=9 | - | - | | 15 | VDDIO\_1 | DI/DO | GPIO\_10 | 7 | uart\_sig\_10\_sel=10 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 15 | VDDIO\_1 | DI/DO | GPIO\_10 | 7 | uart\_sig\_10\_sel=11 | ISO11898\_RXD | CAN (ISO 11898) Receive Data | | 15 | VDDIO\_1 | DI/DO | GPIO\_10 | 8 | - | - | - | | 15 | VDDIO\_1 | DI/DO | GPIO\_10 | 9 | - | CAM1\_DAT1 | Camera 1 Data 1 | | 15 | VDDIO\_1 | DI/DO | GPIO\_10 | 10 | - | ADC\_CH7 | ADC Channel 7 | | 15 | VDDIO\_1 | DI/DO | GPIO\_10 | 11 | - | SWGPIO10 | Software GPIO 10 | | 15 | VDDIO\_1 | DI/DO | GPIO\_10 | 12 | - | SDIO\_DAT2 | SDIO Data 2 | | 15 | VDDIO\_1 | DI/DO | GPIO\_10 | 16 | reg\_pwm1\_io\_sel=0 | PWM0\_CH2P | PWM 0 Channel 2 Positive | | 15 | VDDIO\_1 | DI/DO | GPIO\_10 | 16 | reg\_pwm1\_io\_sel=1 | PWM0\_CH1P | PWM 0 Channel 1 Positive | | 15 | VDDIO\_1 | DI/DO | GPIO\_10 | 22 | - | DBI\_TypeB\_DB2 | Display Bus Interface Type B Data Bit 2 | | 15 | VDDIO\_1 | DI/DO | GPIO\_10 | 23 | - | DBI\_TypeC\_SDA0 | Display Bus Interface Type C Serial Data 0 | | 15 | VDDIO\_1 | DI/DO | GPIO\_10 | 24 | - | DISP\_QSPI\_SCL | Display Quad SPI Serial Clock | | 15 | VDDIO\_1 | DI/DO | GPIO\_10 | 25 | - | - | | | 15 | VDDIO\_1 | DI/DO | GPIO\_10 | 26 | - | M0\_JTAG\_TDO | M0 JTAG Test Data Out | | 16 | VDDIO\_1 | DI/DO | GPIO\_11 | 0 | | SDH\_DAT0 | SD Host Data 0 | | 16 | VDDIO\_1 | DI/DO | GPIO\_11 | 1 | - | SPI\_MOSI | SPI Master Output, Slave Input | | 16 | VDDIO\_1 | DI/DO | GPIO\_11 | 2 | - | SF3\_CLK | SF3 Clock | | 16 | VDDIO\_1 | DI/DO | GPIO\_11 | 3 | - | I2S\_DO/I2S\_RCLK\_O | I^2^S Data Output/I^2^S Receive Clock
Output | | 16 | VDDIO\_1 | DI/DO | GPIO\_11 | 4 | - | - | - | | 16 | VDDIO\_1 | DI/DO | GPIO\_11 | 5 | - | I2C0\_SDA | I^2^C 0 Serial Data | | 16 | VDDIO\_1 | DI/DO | GPIO\_11 | 6 | - | I2C1\_SDA | I^2^C 1 Serial Data | | 16 | VDDIO\_1 | DI/DO | GPIO\_11 | 7 | uart\_sig\_11\_sel=0 | UART0\_RTS | UART 0 Request To Send | | 16 | VDDIO\_1 | DI/DO | GPIO\_11 | 7 | uart\_sig\_11\_sel=1 | UART0\_CTS | UART 0 Clear To Send | | 16 | VDDIO\_1 | DI/DO | GPIO\_11 | 7 | uart\_sig\_11\_sel=2 | UART0\_TXD | UART 0 Transmit Data | | 16 | VDDIO\_1 | DI/DO | GPIO\_11 | 7 | uart\_sig\_11\_sel=3 | UART0\_RXD | UART 0 Receive Data | | 16 | VDDIO\_1 | DI/DO | GPIO\_11 | 7 | uart\_sig\_11\_sel=4 | UART1\_RTS | UART 1 Request To Send | | 16 | VDDIO\_1 | DI/DO | GPIO\_11 | 7 | uart\_sig\_11\_sel=5 | UART1\_CTS | UART 1 Clear To Send | | 16 | VDDIO\_1 | DI/DO | GPIO\_11 | 7 | uart\_sig\_11\_sel=6 | UART1\_TXD | UART 1 Transmit Data | | 16 | VDDIO\_1 | DI/DO | GPIO\_11 | 7 | uart\_sig\_11\_sel=7 | UART1\_RXD | UART 1 Receive Data | | 16 | VDDIO\_1 | DI/DO | GPIO\_11 | 7 | uart\_sig\_11\_sel=8 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 16 | VDDIO\_1 | DI/DO | GPIO\_11 | 7 | uart\_sig\_11\_sel=9 | - | - | | 16 | VDDIO\_1 | DI/DO | GPIO\_11 | 7 | uart\_sig\_11\_sel=10 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 16 | VDDIO\_1 | DI/DO | GPIO\_11 | 7 | uart\_sig\_11\_sel=11 | ISO11898\_RXD | CAN (ISO 11898) Receive Data | | 16 | VDDIO\_1 | DI/DO | GPIO\_11 | 8 | - | - | - | | 16 | VDDIO\_1 | DI/DO | GPIO\_11 | 9 | - | CAM1\_DAT2 | Camera 1 Data 2 | | 16 | VDDIO\_1 | DI/DO | GPIO\_11 | 10 | - | - | - | | 16 | VDDIO\_1 | DI/DO | GPIO\_11 | 11 | - | SWGPIO11 | Software GPIO 11 | | 16 | VDDIO\_1 | DI/DO | GPIO\_11 | 12 | - | SDIO\_DAT3 | SDIO Data 3 | | 16 | VDDIO\_1 | DI/DO | GPIO\_11 | 16 | reg\_pwm1\_io\_sel=0 | PWM0\_CH3P | PWM 0 Channel 3 Positive | | 16 | VDDIO\_1 | DI/DO | GPIO\_11 | 16 | reg\_pwm1\_io\_sel=1 | PWM0\_CH1N | PWM 0 Channel 1 Negative | | 16 | VDDIO\_1 | DI/DO | GPIO\_11 | 22 | - | DBI\_TypeB\_DB3 | Display Bus Interface Type B Data Bit 3 | | 16 | VDDIO\_1 | DI/DO | GPIO\_11 | 23 | - | DBI\_TypeC\_DCn | Display Bus Interface Type C Data/Command Control | | 16 | VDDIO\_1 | DI/DO | GPIO\_11 | 24 | - | DISP\_QSPI\_CSn | Display Quad SPI Chip Select | | 16 | VDDIO\_1 | DI/DO | GPIO\_11 | 25 | - | - | - | | 16 | VDDIO\_1 | DI/DO | GPIO\_11 | 26 | - | M0\_JTAG\_TDI | M0 JTAG Test Data Input | | 17 | VDDIO\_1 | DI/DO | GPIO\_12 | 0 | | SDH\_CLK | SD Host Clock | | 17 | VDDIO\_1 | DI/DO | GPIO\_12 | 1 | - | SPI\_SS | SPI Slave Select | | 17 | VDDIO\_1 | DI/DO | GPIO\_12 | 2 | - | SF3\_D0 | SF3 Data0 | | 17 | VDDIO\_1 | DI/DO | GPIO\_12 | 3 | - | I2S\_BCLK | I^2^S Bit Clock | | 17 | VDDIO\_1 | DI/DO | GPIO\_12 | 4 | - | - | - | | 17 | VDDIO\_1 | DI/DO | GPIO\_12 | 5 | - | I2C0\_SCL | I^2^C 0 Serial Clock | | 17 | VDDIO\_1 | DI/DO | GPIO\_12 | 6 | - | I2C1\_SCL | I^2^C 1 Serial Clock | | 17 | VDDIO\_1 | DI/DO | GPIO\_12 | 7 | uart\_sig\_0\_sel=0 | UART0\_RTS | UART 0 Request To Send | | 17 | VDDIO\_1 | DI/DO | GPIO\_12 | 7 | uart\_sig\_0\_sel=1 | UART0\_CTS | UART 0 Clear To Send | | 17 | VDDIO\_1 | DI/DO | GPIO\_12 | 7 | uart\_sig\_0\_sel=2 | UART0\_TXD | UART 0 Transmit Data | | 17 | VDDIO\_1 | DI/DO | GPIO\_12 | 7 | uart\_sig\_0\_sel=3 | UART0\_RXD | UART 0 Receive Data | | 17 | VDDIO\_1 | DI/DO | GPIO\_12 | 7 | uart\_sig\_0\_sel=4 | UART1\_RTS | UART 1 Request To Send | | 17 | VDDIO\_1 | DI/DO | GPIO\_12 | 7 | uart\_sig\_0\_sel=5 | UART1\_CTS | UART 1 Clear To Send | | 17 | VDDIO\_1 | DI/DO | GPIO\_12 | 7 | uart\_sig\_0\_sel=6 | UART1\_TXD | UART 1 Transmit Data | | 17 | VDDIO\_1 | DI/DO | GPIO\_12 | 7 | uart\_sig\_0\_sel=7 | UART1\_RXD | UART 1 Receive Data | | 17 | VDDIO\_1 | DI/DO | GPIO\_12 | 7 | uart\_sig\_0\_sel=8 | ISO11898\_TXD | CAN (ISO11898) Transmit Data | | 17 | VDDIO\_1 | DI/DO | GPIO\_12 | 7 | uart\_sig\_0\_sel=9 | - | - | | 17 | VDDIO\_1 | DI/DO | GPIO\_12 | 7 | uart\_sig\_0\_sel=10 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 17 | VDDIO\_1 | DI/DO | GPIO\_12 | 7 | uart\_sig\_0\_sel=11 | ISO11898\_RXD | CAN (ISO 11898) Receive Data | | 17 | VDDIO\_1 | DI/DO | GPIO\_12 | 8 | - | - | - | | 17 | VDDIO\_1 | DI/DO | GPIO\_12 | 9 | - | CAM1\_DAT3 | Camera 1 Data 3 | | 17 | VDDIO\_1 | DI/DO | GPIO\_12 | 10 | - | ADC\_CH6 | ADC Channel 6 | | 17 | VDDIO\_1 | DI/DO | GPIO\_12 | 11 | - | SWGPIO12 | Software GPIO 12 | | 17 | VDDIO\_1 | DI/DO | GPIO\_12 | 12 | - | SDIO\_CMD | SDIO Command | | 17 | VDDIO\_1 | DI/DO | GPIO\_12 | 16 | reg\_pwm1\_io\_sel=0 | PWM0\_CH0P | PWM 0 Channel 0 Positive | | 17 | VDDIO\_1 | DI/DO | GPIO\_12 | 16 | reg\_pwm1\_io\_sel=1 | PWM0\_CH2P | PWM 0 Channel 2 Positive | | 17 | VDDIO\_1 | DI/DO | GPIO\_12 | 22 | - | DBI\_TypeB\_DB4 | Display Bus Interface Type B Data Bit 4 | | 17 | VDDIO\_1 | DI/DO | GPIO\_12 | 23 | - | DBI\_TypeC\_SCL | Display Bus Interface Type C Serial Clock | | 17 | VDDIO\_1 | DI/DO | GPIO\_12 | 24 | - | DISP\_QSPI\_SDA0 | Display Quad SPI Serial Data 0 | | 17 | VDDIO\_1 | DI/DO | GPIO\_12 | 25 | - | - | - | | 17 | VDDIO\_1 | DI/DO | GPIO\_12 | 26 | - | M0\_JTAG\_TMS | M0 JTAG Test Mode Select | | 18 | VDDIO\_1 | DI/DO | GPIO\_13 | 0 | - | SDH\_CMD | SD Host Command | | 18 | VDDIO\_1 | DI/DO | GPIO\_13 | 1 | - | SPI\_SCLK | SPI Serial Clock | | 18 | VDDIO\_1 | DI/DO | GPIO\_13 | 2 | - | SF3\_D2 | SF3 Data2 | | 18 | VDDIO\_1 | DI/DO | GPIO\_13 | 3 | - | I2S\_FS | I^2^S Frame Sync | | 18 | VDDIO\_1 | DI/DO | GPIO\_13 | 4 | - | - | - | | 18 | VDDIO\_1 | DI/DO | GPIO\_13 | 5 | - | I2C0\_SDA | I^2^C 0 Serial Data | | 18 | VDDIO\_1 | DI/DO | GPIO\_13 | 6 | - | I2C1\_SDA | I^2^C 1 Serial Data | | 18 | VDDIO\_1 | DI/DO | GPIO\_13 | 7 | uart\_sig\_1\_sel=0 | UART0\_RTS | UART 0 Request To Send | | 18 | VDDIO\_1 | DI/DO | GPIO\_13 | 7 | uart\_sig\_1\_sel=1 | UART0\_CTS | UART 0 Clear To Send | | 18 | VDDIO\_1 | DI/DO | GPIO\_13 | 7 | uart\_sig\_1\_sel=2 | UART0\_TXD | UART 0 Transmit Data | | 18 | VDDIO\_1 | DI/DO | GPIO\_13 | 7 | uart\_sig\_1\_sel=3 | UART0\_RXD | UART 0 Receive Data | | 18 | VDDIO\_1 | DI/DO | GPIO\_13 | 7 | uart\_sig\_1\_sel=4 | UART1\_RTS | UART 1 Request To Send | | 18 | VDDIO\_1 | DI/DO | GPIO\_13 | 7 | uart\_sig\_1\_sel=5 | UART1\_CTS | UART 1 Clear To Send | | 18 | VDDIO\_1 | DI/DO | GPIO\_13 | 7 | uart\_sig\_1\_sel=6 | UART1\_TXD | UART 1 Transmit Data | | 18 | VDDIO\_1 | DI/DO | GPIO\_13 | 7 | uart\_sig\_1\_sel=7 | UART1\_RXD | UART 1 Receive Data | | 18 | VDDIO\_1 | DI/DO | GPIO\_13 | 7 | uart\_sig\_1\_sel=8 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 18 | VDDIO\_1 | DI/DO | GPIO\_13 | 7 | uart\_sig\_1\_sel=9 | - | - | | 18 | VDDIO\_1 | DI/DO | GPIO\_13 | 7 | uart\_sig\_1\_sel=10 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 18 | VDDIO\_1 | DI/DO | GPIO\_13 | 7 | uart\_sig\_1\_sel=11 | ISO11898\_RXD | CAN (ISO 11898) Receive Data | | 18 | VDDIO\_1 | DI/DO | GPIO\_13 | 8 | - | - | - | | 18 | VDDIO\_1 | DI/DO | GPIO\_13 | 9 | - | CAM1\_CLK | Camera 1 Clock | | 18 | VDDIO\_1 | DI/DO | GPIO\_13 | 10 | - | ADC\_CH5 | ADC Channel 5 | | 18 | VDDIO\_1 | DI/DO | GPIO\_13 | 11 | - | SWGPIO13 | Software GPIO 13 | | 18 | VDDIO\_1 | DI/DO | GPIO\_13 | 12 | - | SDIO\_CLK | SDIO Clock | | 18 | VDDIO\_1 | DI/DO | GPIO\_13 | 16 | reg\_pwm1\_io\_sel=0 | PWM0\_CH1P | PWM 0 Channel 1 Positive | | 18 | VDDIO\_1 | DI/DO | GPIO\_13 | 16 | reg\_pwm1\_io\_sel=1 | PWM0\_CH2N | PWM 0 Channel 2 Negative | | 18 | VDDIO\_1 | DI/DO | GPIO\_13 | 22 | - | DBI\_TypeB\_DB5 | Display Bus Interface Type B Data Bit 5 | | 18 | VDDIO\_1 | DI/DO | GPIO\_13 | 23 | - | DBI\_TypeC\_CSn | Display Bus Interface Type C Chip Select | | 18 | VDDIO\_1 | DI/DO | GPIO\_13 | 24 | - | DISP\_QSPI\_SDA1 | Display Quad SPI Serial Data 1 | | 18 | VDDIO\_1 | DI/DO | GPIO\_13 | 25 | - | - | - | | 18 | VDDIO\_1 | DI/DO | GPIO\_13 | 26 | - | M0\_JTAG\_TCK | M0 JTAG Test Clock | | 19 | VDDIO\_1 | DI/DO | GPIO\_14 | 0 | | SDH\_DAT3 | SD Host Data 3 | | 19 | VDDIO\_1 | DI/DO | GPIO\_14 | 1 | - | SPI\_MISO | SPI Master Input, Slave Output | | 19 | VDDIO\_1 | DI/DO | GPIO\_14 | 2 | - | SF3\_D1 | SF3 Data 1 | | 19 | VDDIO\_1 | DI/DO | GPIO\_14 | 3 | - | I2S\_DI/I2S\_RCLK\_O | I^2^S Data Input/I^2^S Receive Clock Output | | 19 | VDDIO\_1 | DI/DO | GPIO\_14 | 4 | - | - | - | | 19 | VDDIO\_1 | DI/DO | GPIO\_14 | 5 | - | I2C0\_SCL | I^2^C 0 Serial Clock | | 19 | VDDIO\_1 | DI/DO | GPIO\_14 | 6 | - | I2C1\_SCL | I^2^C 1 Serial Clock | | 19 | VDDIO\_1 | DI/DO | GPIO\_14 | 7 | uart\_sig\_2\_sel=0 | UART0\_RTS | UART 0 Request To Send | | 19 | VDDIO\_1 | DI/DO | GPIO\_14 | 7 | uart\_sig\_2\_sel=1 | UART0\_CTS | UART 0 Clear To Send | | 19 | VDDIO\_1 | DI/DO | GPIO\_14 | 7 | uart\_sig\_2\_sel=2 | UART0\_TXD | UART 0 Transmit Data | | 19 | VDDIO\_1 | DI/DO | GPIO\_14 | 7 | uart\_sig\_2\_sel=3 | UART0\_RXD | UART 0 Receive Data | | 19 | VDDIO\_1 | DI/DO | GPIO\_14 | 7 | uart\_sig\_2\_sel=4 | UART1\_RTS | UART 1 Request To Send | | 19 | VDDIO\_1 | DI/DO | GPIO\_14 | 7 | uart\_sig\_2\_sel=5 | UART1\_CTS | UART 1 Clear To Send | | 19 | VDDIO\_1 | DI/DO | GPIO\_14 | 7 | uart\_sig\_2\_sel=6 | UART1\_TXD | UART 1 Transmit Data | | 19 | VDDIO\_1 | DI/DO | GPIO\_14 | 7 | uart\_sig\_2\_sel=7 | UART1\_RXD | UART 1 Receive Data | | 19 | VDDIO\_1 | DI/DO | GPIO\_14 | 7 | uart\_sig\_2\_sel=8 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 19 | VDDIO\_1 | DI/DO | GPIO\_14 | 7 | uart\_sig\_2\_sel=9 | - | - | | 19 | VDDIO\_1 | DI/DO | GPIO\_14 | 7 | uart\_sig\_2\_sel=10 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 19 | VDDIO\_1 | DI/DO | GPIO\_14 | 7 | uart\_sig\_2\_sel=11 | ISO11898\_RXD | CAN (ISO 11898) Receive Data | | 19 | VDDIO\_1 | DI/DO | GPIO\_14 | 8 | - | - | - | | 19 | VDDIO\_1 | DI/DO | GPIO\_14 | 9 | - | CAM1\_DAT4 | Camera 1 Data 4 | | 19 | VDDIO\_1 | DI/DO | GPIO\_14 | 10 | - | ADC\_CH4 | ADC Channel 4 | | 19 | VDDIO\_1 | DI/DO | GPIO\_14 | 11 | - | SWGPIO14 | Software GPIO 14 | | 19 | VDDIO\_1 | DI/DO | GPIO\_14 | 12 | - | SDIO\_DAT0 | SDIO Data 0 | | 19 | VDDIO\_1 | DI/DO | GPIO\_14 | 16 | reg\_pwm1\_io\_sel=0 | PWM0\_CH2P | PWM 0 Channel 2 Positive | | 19 | VDDIO\_1 | DI/DO | GPIO\_14 | 16 | reg\_pwm1\_io\_sel=1 | PWM0\_CH3P | PWM 0 Channel 3 Positive | | 19 | VDDIO\_1 | DI/DO | GPIO\_14 | 22 | - | DBI\_TypeB\_DB6 | Display Bus Interface Type B Data Bit 6 | | 19 | VDDIO\_1 | DI/DO | GPIO\_14 | 23 | - | DBI\_TypeC\_SDA0 | Display Bus Interface Type C Serial Data 0 | | 19 | VDDIO\_1 | DI/DO | GPIO\_14 | 24 | - | DISP\_QSPI\_SDA2 | Display Quad SPI Serial Data 2 | | 19 | VDDIO\_1 | DI/DO | GPIO\_14 | 25 | - | AUDAC\_PWM\_P | AUDAC\_PWM\_P | | 19 | VDDIO\_1 | DI/DO | GPIO\_14 | 26 | - | M0\_JTAG\_TDO | M0 JTAG Test Data Out | | 20 | VDDIO\_1 | DI/DO | GPIO\_15 | 0 | | SDH\_DAT2 | SD Host Data 2 | | 20 | VDDIO\_1 | DI/DO | GPIO\_15 | 1 | - | SPI\_MOSI | SPI Master Output, Slave Input | | 20 | VDDIO\_1 | DI/DO | GPIO\_15 | 2 | - | SF3\_CS | SF3 Chip Select | | 20 | VDDIO\_1 | DI/DO | GPIO\_15 | 3 | - | I2S\_DO/I2S\_RCLK\_O | I^2^S Data Output/I^2^S Receive Clock
Output | | 20 | VDDIO\_1 | DI/DO | GPIO\_15 | 4 | - | - | - | | 20 | VDDIO\_1 | DI/DO | GPIO\_15 | 5 | - | I2C0\_SDA | I^2^C 0 Serial Data | | 20 | VDDIO\_1 | DI/DO | GPIO\_15 | 6 | - | I2C1\_SDA | I^2^C 1 Serial Data | | 20 | VDDIO\_1 | DI/DO | GPIO\_15 | 7 | uart\_sig\_3\_sel=0 | UART0\_RTS | UART 0 Request To Send | | 20 | VDDIO\_1 | DI/DO | GPIO\_15 | 7 | uart\_sig\_3\_sel=1 | UART0\_CTS | UART 0 Clear To Send | | 20 | VDDIO\_1 | DI/DO | GPIO\_15 | 7 | uart\_sig\_3\_sel=2 | UART0\_TXD | UART 0 Transmit Data | | 20 | VDDIO\_1 | DI/DO | GPIO\_15 | 7 | uart\_sig\_3\_sel=3 | UART0\_RXD | UART 0 Receive Data | | 20 | VDDIO\_1 | DI/DO | GPIO\_15 | 7 | uart\_sig\_3\_sel=4 | UART1\_RTS | UART 1 Request To Send | | 20 | VDDIO\_1 | DI/DO | GPIO\_15 | 7 | uart\_sig\_3\_sel=5 | UART1\_CTS | UART 1 Clear To Send | | 20 | VDDIO\_1 | DI/DO | GPIO\_15 | 7 | uart\_sig\_3\_sel=6 | UART1\_TXD | UART 1 Transmit Data | | 20 | VDDIO\_1 | DI/DO | GPIO\_15 | 7 | uart\_sig\_3\_sel=7 | UART1\_RXD | UART 1 Receive Data | | 20 | VDDIO\_1 | DI/DO | GPIO\_15 | 7 | uart\_sig\_3\_sel=8 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 20 | VDDIO\_1 | DI/DO | GPIO\_15 | 7 | uart\_sig\_3\_sel=9 | - | - | | 20 | VDDIO\_1 | DI/DO | GPIO\_15 | 7 | uart\_sig\_3\_sel=10 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 20 | VDDIO\_1 | DI/DO | GPIO\_15 | 7 | uart\_sig\_3\_sel=11 | ISO11898\_RXD | CAN (ISO 11898) Receive Data | | 20 | VDDIO\_1 | DI/DO | GPIO\_15 | 8 | - | - | - | | 20 | VDDIO\_1 | DI/DO | GPIO\_15 | 9 | - | CAM1\_DAT5 | Camera 1 Data 5 | | 20 | VDDIO\_1 | DI/DO | GPIO\_15 | 10 | - | - | - | | 20 | VDDIO\_1 | DI/DO | GPIO\_15 | 11 | - | SWGPIO15 | Software GPIO 15 | | 20 | VDDIO\_1 | DI/DO | GPIO\_15 | 12 | - | SDIO\_DAT1 | SDIO Data 1 | | 20 | VDDIO\_1 | DI/DO | GPIO\_15 | 16 | reg\_pwm1\_io\_sel=0 | PWM0\_CH3P | PWM 0 Channel 3 Positive | | 20 | VDDIO\_1 | DI/DO | GPIO\_15 | 16 | reg\_pwm1\_io\_sel=1 | PWM0\_CH3N | PWM 0 Channel 3 Negative | | 20 | VDDIO\_1 | DI/DO | GPIO\_15 | 22 | - | DBI\_TypeB\_DB7 | Display Bus Interface Type B Data Bit 7 | | 20 | VDDIO\_1 | DI/DO | GPIO\_15 | 23 | - | DBI\_TypeC\_DCn | Display Bus Interface Type C Data/Command Control | | 20 | VDDIO\_1 | DI/DO | GPIO\_15 | 24 | - | DISP\_QSPI\_SDA3 | Display Quad SPI Serial Data 3 | | 20 | VDDIO\_1 | DI/DO | GPIO\_15 | 25 | - | AUDAC\_PWM\_N | AUDAC\_PWM\_N | | 20 | VDDIO\_1 | DI/DO | GPIO\_15 | 26 | - | M0\_JTAG\_TDI | M0 JTAG Test Data Input | | 21 | AVDD33\_AON | DI/DO | GPIO\_16 | - | - | - | - | | 21 | AVDD33\_AON | DI/DO | GPIO\_16 | 1 | - | SPI\_SS | SPI Slave Select | | 21 | AVDD33\_AON | DI/DO | GPIO\_16 | 2 | - | - | - | | 21 | AVDD33\_AON | DI/DO | GPIO\_16 | 3 | - | I2S\_BCLK | I^2^S Bit Clock | | 21 | AVDD33\_AON | DI/DO | GPIO\_16 | 4 | - | - | - | | 21 | AVDD33\_AON | DI/DO | GPIO\_16 | 5 | - | I2C0\_SCL | I^2^C 0 Serial Clock | | 21 | AVDD33\_AON | DI/DO | GPIO\_16 | 6 | - | I2C1\_SCL | I^2^C 1 Serial Clock | | 21 | AVDD33\_AON | DI/DO | GPIO\_16 | 7 | uart\_sig\_4\_sel=0 | UART0\_RTS | UART 0 Request To Send | | 21 | AVDD33\_AON | DI/DO | GPIO\_16 | 7 | uart\_sig\_4\_sel=1 | UART0\_CTS | UART 0 Clear To Send | | 21 | AVDD33\_AON | DI/DO | GPIO\_16 | 7 | uart\_sig\_4\_sel=2 | UART0\_TXD | UART 0 Transmit Data | | 21 | AVDD33\_AON | DI/DO | GPIO\_16 | 7 | uart\_sig\_4\_sel=3 | UART0\_RXD | UART 0 Receive Data | | 21 | AVDD33\_AON | DI/DO | GPIO\_16 | 7 | uart\_sig\_4\_sel=4 | UART1\_RTS | UART 1 Request To Send | | 21 | AVDD33\_AON | DI/DO | GPIO\_16 | 7 | uart\_sig\_4\_sel=5 | UART1\_CTS | UART 1 Clear To Send | | 21 | AVDD33\_AON | DI/DO | GPIO\_16 | 7 | uart\_sig\_4\_sel=6 | UART1\_TXD | UART 1 Transmit Data | | 21 | AVDD33\_AON | DI/DO | GPIO\_16 | 7 | uart\_sig\_4\_sel=7 | UART1\_RXD | UART 1 Receive Data | | 21 | AVDD33\_AON | DI/DO | GPIO\_16 | 7 | uart\_sig\_4\_sel=8 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 21 | AVDD33\_AON | DI/DO | GPIO\_16 | 7 | uart\_sig\_4\_sel=9 | - | - | | 21 | AVDD33\_AON | DI/DO | GPIO\_16 | 7 | uart\_sig\_4\_sel=10 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 21 | AVDD33\_AON | DI/DO | GPIO\_16 | 7 | uart\_sig\_4\_sel=11 | ISO11898\_RXD | CAN (ISO11898) Receive Data | | 21 | AVDD33\_AON | DI/DO | GPIO\_16 | 8 | - | - | - | | 21 | AVDD33\_AON | DI/DO | GPIO\_16 | 9 | - | CAM1\_DAT6 | Camera 1 Data 6 | | 21 | AVDD33\_AON | DI/DO | GPIO\_16 | 10 | - | - | - | | 21 | AVDD33\_AON | DI/DO | GPIO\_16 | 11 | - | SWGPIO16 | Software GPIO 16 | | 21 | AVDD33\_AON | DI/DO | GPIO\_16 | 12 | - | - | - | | 21 | AVDD33\_AON | DI/DO | GPIO\_16 | 16 | reg\_pwm1\_io\_sel=0 | PWM0\_CH0P | PWM 0 Channel 0 Positive | | 21 | AVDD33\_AON | DI/DO | GPIO\_16 | 16 | reg\_pwm1\_io\_sel=1 | PWM0\_CH0P | PWM 0 Channel 0 Positive | | 21 | AVDD33\_AON | DI/DO | GPIO\_16 | 22 | - | - | - | | 21 | AVDD33\_AON | DI/DO | GPIO\_16 | 23 | - | - | - | | 21 | AVDD33\_AON | DI/DO | GPIO\_16 | 24 | - | - | - | | 21 | AVDD33\_AON | DI/DO | GPIO\_16 | 25 | - | - | - | | 21 | AVDD33\_AON | DI/DO | GPIO\_16 | 26 | - | M0\_JTAG\_TMS | M0 JTAG Test Mode Select | | 22 | AVDD33\_AON | DI/DO | GPIO\_17 | 0 | - | - | - | | 22 | AVDD33\_AON | DI/DO | GPIO\_17 | 1 | - | SPI\_SCLK | SPI Serial Clock | | 22 | AVDD33\_AON | DI/DO | GPIO\_17 | 2 | - | - | - | | 22 | AVDD33\_AON | DI/DO | GPIO\_17 | 3 | - | I2S\_FS | I^2^S Frame Sync | | 22 | AVDD33\_AON | DI/DO | GPIO\_17 | 4 | - | - | - | | 22 | AVDD33\_AON | DI/DO | GPIO\_17 | 5 | - | I2C0\_SDA | I^2^C 0 Serial Data | | 22 | AVDD33\_AON | DI/DO | GPIO\_17 | 6 | - | I2C1\_SDA | I^2^C 1 Serial Data | | 22 | AVDD33\_AON | DI/DO | GPIO\_17 | 7 | uart\_sig\_5\_sel=0 | UART0\_RTS | UART 0 Request To Send | | 22 | AVDD33\_AON | DI/DO | GPIO\_17 | 7 | uart\_sig\_5\_sel=1 | UART0\_CTS | UART 0 Clear To Send | | 22 | AVDD33\_AON | DI/DO | GPIO\_17 | 7 | uart\_sig\_5\_sel=2 | UART0\_TXD | UART 0 Transmit Data | | 22 | AVDD33\_AON | DI/DO | GPIO\_17 | 7 | uart\_sig\_5\_sel=3 | UART0\_RXD | UART 0 Receive Data | | 22 | AVDD33\_AON | DI/DO | GPIO\_17 | 7 | uart\_sig\_5\_sel=4 | UART1\_RTS | UART 1 Request To Send | | 22 | AVDD33\_AON | DI/DO | GPIO\_17 | 7 | uart\_sig\_5\_sel=5 | UART1\_CTS | UART 1 Clear To Send | | 22 | AVDD33\_AON | DI/DO | GPIO\_17 | 7 | uart\_sig\_5\_sel=6 | UART1\_TXD | UART 1 Transmit Data | | 22 | AVDD33\_AON | DI/DO | GPIO\_17 | 7 | uart\_sig\_5\_sel=7 | UART1\_RXD | UART 1 Receive Data | | 22 | AVDD33\_AON | DI/DO | GPIO\_17 | 7 | uart\_sig\_5\_sel=8 | ISO11898\_TXD | CAN (ISO11898) Transmit Data | | 22 | AVDD33\_AON | DI/DO | GPIO\_17 | 7 | uart\_sig\_5\_sel=9 | - | - | | 22 | AVDD33\_AON | DI/DO | GPIO\_17 | 7 | uart\_sig\_5\_sel=10 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 22 | AVDD33\_AON | DI/DO | GPIO\_17 | 7 | uart\_sig\_5\_sel=11 | ISO11898\_RXD | CAN (ISO 11898) Receive Data | | 22 | AVDD33\_AON | DI/DO | GPIO\_17 | 8 | - | - | - | | 22 | AVDD33\_AON | DI/DO | GPIO\_17 | 9 | - | CAM1\_DAT7 | Camera 1 Data 7 | | 22 | AVDD33\_AON | DI/DO | GPIO\_17 | 10 | - | - | - | | 22 | AVDD33\_AON | DI/DO | GPIO\_17 | 11 | - | SWGPIO17 | Software GPIO 17 | | 22 | AVDD33\_AON | DI/DO | GPIO\_17 | 12 | - | - | - | | 22 | AVDD33\_AON | DI/DO | GPIO\_17 | 16 | reg\_pwm1\_io\_sel=0 | PWM0\_CH1P | PWM 0 Channel 1 Positive | | 22 | AVDD33\_AON | DI/DO | GPIO\_17 | 16 | reg\_pwm1\_io\_sel=1 | PWM0\_CH0N | PWM 0 Channel 0 Negative | | 22 | AVDD33\_AON | DI/DO | GPIO\_17 | 22 | - | - | - | | 22 | AVDD33\_AON | DI/DO | GPIO\_17 | 23 | - | - | - | | 22 | AVDD33\_AON | DI/DO | GPIO\_17 | 24 | - | - | - | | 22 | AVDD33\_AON | DI/DO | GPIO\_17 | 25 | - | - | - | | 22 | AVDD33\_AON | DI/DO | GPIO\_17 | 26 | - | M0\_JTAG\_TCK | M0 JTAG Test Clock | | 23 | AVDD33\_AON | DI/DO | GPIO\_18 | 0 | - | - | - | | 23 | AVDD33\_AON | DI/DO | GPIO\_18 | 1 | - | SPI\_MISO | SPI Master Input, Slave Output | | 23 | AVDD33\_AON | DI/DO | GPIO\_18 | 2 | - | - | | | 23 | AVDD33\_AON | DI/DO | GPIO\_18 | 3 | - | I2S\_DI/I2S\_RCLK\_O | I^2^S Data Input/I^2^S Receive Clock Output | | 23 | AVDD33\_AON | DI/DO | GPIO\_18 | 4 | - | - | - | | 23 | AVDD33\_AON | DI/DO | GPIO\_18 | 5 | - | I2C0\_SCL | I^2^C 0 Serial Clock | | 23 | AVDD33\_AON | DI/DO | GPIO\_18 | 6 | - | I2C1\_SCL | I^2^C 1 Serial Clock | | 23 | AVDD33\_AON | DI/DO | GPIO\_18 | 7 | uart\_sig\_6\_sel=0 | UART0\_RTS | UART 0 Request To Send | | 23 | AVDD33\_AON | DI/DO | GPIO\_18 | 7 | uart\_sig\_6\_sel=1 | UART0\_CTS | UART 0 Clear To Send | | 23 | AVDD33\_AON | DI/DO | GPIO\_18 | 7 | uart\_sig\_6\_sel=2 | UART0\_TXD | UART 0 Transmit Data | | 23 | AVDD33\_AON | DI/DO | GPIO\_18 | 7 | uart\_sig\_6\_sel=3 | UART0\_RXD | UART 0 Receive Data | | 23 | AVDD33\_AON | DI/DO | GPIO\_18 | 7 | uart\_sig\_6\_sel=4 | UART1\_RTS | UART 1 Request To Send | | 23 | AVDD33\_AON | DI/DO | GPIO\_18 | 7 | uart\_sig\_6\_sel=5 | UART1\_CTS | UART 1 Clear To Send | | 23 | AVDD33\_AON | DI/DO | GPIO\_18 | 7 | uart\_sig\_6\_sel=6 | UART1\_TXD | UART 1 Transmit Data | | 23 | AVDD33\_AON | DI/DO | GPIO\_18 | 7 | uart\_sig\_6\_sel=7 | UART1\_RXD | UART 1 Receive Data | | 23 | AVDD33\_AON | DI/DO | GPIO\_18 | 7 | uart\_sig\_6\_sel=8 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 23 | AVDD33\_AON | DI/DO | GPIO\_18 | 7 | uart\_sig\_6\_sel=9 | - | - | | 23 | AVDD33\_AON | DI/DO | GPIO\_18 | 7 | uart\_sig\_6\_sel=10 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 23 | AVDD33\_AON | DI/DO | GPIO\_18 | 7 | uart\_sig\_6\_sel=11 | ISO11898\_RXD | CAN (ISO 11898) Receive Data | | 23 | AVDD33\_AON | DI/DO | GPIO\_18 | 8 | - | - | - | | 23 | AVDD33\_AON | DI/DO | GPIO\_18 | 9 | - | - | - | | 23 | AVDD33\_AON | DI/DO | GPIO\_18 | 10 | - | - | - | | 23 | AVDD33\_AON | DI/DO | GPIO\_18 | 11 | - | SWGPIO18 | Software GPIO 18 | | 23 | AVDD33\_AON | DI/DO | GPIO\_18 | 12 | - | - | - | | 23 | AVDD33\_AON | DI/DO | GPIO\_18 | 16 | reg\_pwm1\_io\_sel=0 | PWM0\_CH2P | PWM 0 Channel 2 Positive | | 23 | AVDD33\_AON | DI/DO | GPIO\_18 | 16 | reg\_pwm1\_io\_sel=1 | PWM0\_CH1P | PWM 0 Channel 1 Positive | | 23 | AVDD33\_AON | DI/DO | GPIO\_18 | 22 | - | - | - | | 23 | AVDD33\_AON | DI/DO | GPIO\_18 | 23 | - | - | - | | 23 | AVDD33\_AON | DI/DO | GPIO\_18 | 24 | - | - | - | | 23 | AVDD33\_AON | DI/DO | GPIO\_18 | 25 | - | - | - | | 23 | AVDD33\_AON | DI/DO | GPIO\_18 | 26 | - | M0\_JTAG\_TDO | M0 JTAG Test Data Out | | 24 | AVDD33\_AON | DI/DO | GPIO\_19 | 0 | - | - | - | | 24 | AVDD33\_AON | DI/DO | GPIO\_19 | 1 | - | SPI\_MOSI | SPI Master Output, Slave Input | | 24 | AVDD33\_AON | DI/DO | GPIO\_19 | 2 | - | - | - | | 24 | AVDD33\_AON | DI/DO | GPIO\_19 | 3 | - | I2S\_DO/I2S\_RCLK\_O | I^2^S Data Output/I^2^S Receive Clock
Output | | 24 | AVDD33\_AON | DI/DO | GPIO\_19 | 4 | - | - | - | | 24 | AVDD33\_AON | DI/DO | GPIO\_19 | 5 | - | I2C0\_SDA | I^2^C 0 Serial Data | | 24 | AVDD33\_AON | DI/DO | GPIO\_19 | 6 | - | I2C1\_SDA | I^2^C 1 Serial Data | | 24 | AVDD33\_AON | DI/DO | GPIO\_19 | 7 | uart\_sig\_7\_sel=0 | UART0\_RTS | UART 0 Request To Send | | 24 | AVDD33\_AON | DI/DO | GPIO\_19 | 7 | uart\_sig\_7\_sel=1 | UART0\_CTS | UART 0 Clear To Send | | 24 | AVDD33\_AON | DI/DO | GPIO\_19 | 7 | uart\_sig\_7\_sel=2 | UART0\_TXD | UART 0 Transmit Data | | 24 | AVDD33\_AON | DI/DO | GPIO\_19 | 7 | uart\_sig\_7\_sel=3 | UART0\_RXD | UART 0 Receive Data | | 24 | AVDD33\_AON | DI/DO | GPIO\_19 | 7 | uart\_sig\_7\_sel=4 | UART1\_RTS | UART 1 Request To Send | | 24 | AVDD33\_AON | DI/DO | GPIO\_19 | 7 | uart\_sig\_7\_sel=5 | UART1\_CTS | UART 1 Clear To Send | | 24 | AVDD33\_AON | DI/DO | GPIO\_19 | 7 | uart\_sig\_7\_sel=6 | UART1\_TXD | UART 1 Transmit Data | | 24 | AVDD33\_AON | DI/DO | GPIO\_19 | 7 | uart\_sig\_7\_sel=7 | UART1\_RXD | UART 1 Receive Data | | 24 | AVDD33\_AON | DI/DO | GPIO\_19 | 7 | uart\_sig\_7\_sel=8 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 24 | AVDD33\_AON | DI/DO | GPIO\_19 | 7 | uart\_sig\_7\_sel=9 | - | - | | 24 | AVDD33\_AON | DI/DO | GPIO\_19 | 7 | uart\_sig\_7\_sel=10 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 24 | AVDD33\_AON | DI/DO | GPIO\_19 | 7 | uart\_sig\_7\_sel=11 | ISO11898\_RXD | CAN (ISO 11898) Receive Data | | 24 | AVDD33\_AON | DI/DO | GPIO\_19 | 8 | - | - | - | | 24 | AVDD33\_AON | DI/DO | GPIO\_19 | 9 | - | - | - | | 24 | AVDD33\_AON | DI/DO | GPIO\_19 | 10 | - | ADC\_CH1 | ADC Channel 1 | | 24 | AVDD33\_AON | DI/DO | GPIO\_19 | 11 | - | SWGPIO19 | Software GPIO 19 | | 24 | AVDD33\_AON | DI/DO | GPIO\_19 | 12 | - | - | - | | 24 | AVDD33\_AON | DI/DO | GPIO\_19 | 16 | reg\_pwm1\_io\_sel=0 | PWM0\_CH3P | PWM 0 Channel 3 Positive | | 24 | AVDD33\_AON | DI/DO | GPIO\_19 | 16 | reg\_pwm1\_io\_sel=1 | PWM0\_CH1N | PWM 0 Channel 1 Negative | | 24 | AVDD33\_AON | DI/DO | GPIO\_19 | 22 | - | - | - | | 24 | AVDD33\_AON | DI/DO | GPIO\_19 | 23 | - | - | - | | 24 | AVDD33\_AON | DI/DO | GPIO\_19 | 24 | - | - | - | | 24 | AVDD33\_AON | DI/DO | GPIO\_19 | 25 | - | - | - | | 24 | AVDD33\_AON | DI/DO | GPIO\_19 | 26 | - | M0\_JTAG\_TDI | M0 JTAG Test Data Input | | 25 | AVDD33\_AON | Analog | CHIP\_EN | | | CHIP\_EN | CHIP\_EN | | 26 | - | Power, Input | AVDD33\_AON | - | - | AVDD33\_AON | 3.3 V power supply for always-on circuits | | 27 | - | Power, Output | VDD18\_FLASH | - | - | VDD18\_FLASH | 1.8 V/3.3 V power supply for built-in flash/pSRAM (internal regulator
output) | | 28 | - | Power, Input | PVDD33\_DCDC | - | - | PVDD33\_DCDC | 3.3 V power supply for DCDC | | 29 | - | Power, Output | SW\_DCDC | - | - | SW\_DCDC | Switch PIN of DCDC | | 30 | - | Power,Inout | DCDC\_OUT | - | - | DCDC\_OUT | DCDC output | | 31 | - | Power, Output | DVDD11 | - | - | DVDD11 | Power supply of digital core (internal regulator output) | | 32 | | Power, Input | VDD33\_USB | - | - | VDD33\_USB | 3.3 V power supply of USB and audio ADC | | 33 | VDDIO\_USB | DI/DO | USB\_DP | - | - | USB\_DP | USB Data Plus | | 34 | VDDIO\_USB | DI/DO | USB\_DM | - | - | USB\_DM | USB Data Minus | | 35 | VDDIO\_2 | DI/DO | GPIO\_20 | 0 | - | - | - | | 35 | VDDIO\_2 | DI/DO | GPIO\_20 | 1 | - | SPI\_SS | SPI Slave Select | | 35 | VDDIO\_2 | DI/DO | GPIO\_20 | 2 | - | - | - | | 35 | VDDIO\_2 | DI/DO | GPIO\_20 | 3 | - | I2S\_BCLK | I^2^S Bit Clock | | 35 | VDDIO\_2 | DI/DO | GPIO\_20 | 4 | - | PDM\_CLK\_O | PDM Clock Line | | 35 | VDDIO\_2 | DI/DO | GPIO\_20 | 5 | - | I2C0\_SCL | I^2^C 0 Serial Clock | | 35 | VDDIO\_2 | DI/DO | GPIO\_20 | 6 | - | I2C1\_SCL | I^2^C 1 Serial Clock | | 35 | VDDIO\_2 | DI/DO | GPIO\_20 | 7 | uart\_sig\_8\_sel=0 | UART0\_RTS | UART 0 Request To Send | | 35 | VDDIO\_2 | DI/DO | GPIO\_20 | 7 | uart\_sig\_8\_sel=1 | UART0\_CTS | UART 0 Clear To Send | | 35 | VDDIO\_2 | DI/DO | GPIO\_20 | 7 | uart\_sig\_8\_sel=2 | UART0\_TXD | UART 0 Transmit Data | | 35 | VDDIO\_2 | DI/DO | GPIO\_20 | 7 | uart\_sig\_8\_sel=3 | UART0\_RXD | UART 0 Receive Data | | 35 | VDDIO\_2 | DI/DO | GPIO\_20 | 7 | uart\_sig\_8\_sel=4 | UART1\_RTS | UART 1 Request To Send | | 35 | VDDIO\_2 | DI/DO | GPIO\_20 | 7 | uart\_sig\_8\_sel=5 | UART1\_CTS | UART 1 Clear To Send | | 35 | VDDIO\_2 | DI/DO | GPIO\_20 | 7 | uart\_sig\_8\_sel=6 | UART1\_TXD | UART 1 Transmit Data | | 35 | VDDIO\_2 | DI/DO | GPIO\_20 | 7 | uart\_sig\_8\_sel=7 | UART1\_RXD | UART 1 Receive Data | | 35 | VDDIO\_2 | DI/DO | GPIO\_20 | 7 | uart\_sig\_8\_sel=8 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 35 | VDDIO\_2 | DI/DO | GPIO\_20 | 7 | uart\_sig\_8\_sel=9 | - | - | | 35 | VDDIO\_2 | DI/DO | GPIO\_20 | 7 | uart\_sig\_8\_sel=10 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 35 | VDDIO\_2 | DI/DO | GPIO\_20 | 7 | uart\_sig\_8\_sel=11 | ISO11898\_RXD | CAN (ISO 11898) Receive Data | | 35 | VDDIO\_2 | DI/DO | GPIO\_20 | 8 | - | - | - | | 35 | VDDIO\_2 | DI/DO | GPIO\_20 | 9 | - | - | - | | 35 | VDDIO\_2 | DI/DO | GPIO\_20 | 10 | - | ADC\_CH0/AUADC\_CH0 | ADC Channel 0/ Audio ADC Channel 0 | | 35 | VDDIO\_2 | DI/DO | GPIO\_20 | 11 | - | SWGPIO20 | Software GPIO 20 | | 35 | VDDIO\_2 | DI/DO | GPIO\_20 | 12 | - | - | - | | 35 | VDDIO\_2 | DI/DO | GPIO\_20 | 16 | reg\_pwm1\_io\_sel=0 | PWM0\_CH0P | PWM 0 Channel 0 Positive | | 35 | VDDIO\_2 | DI/DO | GPIO\_20 | 16 | reg\_pwm1\_io\_sel=1 | PWM0\_CH2P | PWM 0 Channel 2 Positive | | 35 | VDDIO\_2 | DI/DO | GPIO\_20 | 22 | - | - | - | | 35 | VDDIO\_2 | DI/DO | GPIO\_20 | 23 | - | - | - | | 35 | VDDIO\_2 | DI/DO | GPIO\_20 | 24 | - | - | - | | 35 | VDDIO\_2 | DI/DO | GPIO\_20 | 25 | - | - | - | | 35 | VDDIO\_2 | DI/DO | GPIO\_20 | 26 | - | M0\_JTAG\_TMS | M0 JTAG Test Mode Select | | 36 | VDDIO\_2 | DI/DO | GPIO\_21 | 0 | - | - | - | | 36 | VDDIO\_2 | DI/DO | GPIO\_21 | 1 | - | SPI\_SCLK | SPI Serial Clock | | 36 | VDDIO\_2 | DI/DO | GPIO\_21 | 2 | - | - | - | | 36 | VDDIO\_2 | DI/DO | GPIO\_21 | 3 | - | I2S\_FS | I^2^S Frame Sync | | 36 | VDDIO\_2 | DI/DO | GPIO\_21 | 4 | - | PDM\_0\_IN | PDM Data Line | | 36 | VDDIO\_2 | DI/DO | GPIO\_21 | 5 | - | I2C0\_SDA | I^2^C 0 Serial Data | | 36 | VDDIO\_2 | DI/DO | GPIO\_21 | 6 | - | I2C1\_SDA | I^2^C 1 Serial Data | | 36 | VDDIO\_2 | DI/DO | GPIO\_21 | 7 | uart\_sig\_9\_sel=0 | UART0\_RTS | UART 0 Request To Send | | 36 | VDDIO\_2 | DI/DO | GPIO\_21 | 7 | uart\_sig\_9\_sel=1 | UART0\_CTS | UART 0 Clear To Send | | 36 | VDDIO\_2 | DI/DO | GPIO\_21 | 7 | uart\_sig\_9\_sel=2 | UART0\_TXD | UART 0 Transmit Data | | 36 | VDDIO\_2 | DI/DO | GPIO\_21 | 7 | uart\_sig\_9\_sel=3 | UART0\_RXD | UART 0 Receive Data | | 36 | VDDIO\_2 | DI/DO | GPIO\_21 | 7 | uart\_sig\_9\_sel=4 | UART1\_RTS | UART 1 Request To Send | | 36 | VDDIO\_2 | DI/DO | GPIO\_21 | 7 | uart\_sig\_9\_sel=5 | UART1\_CTS | UART 1 Clear To Send | | 36 | VDDIO\_2 | DI/DO | GPIO\_21 | 7 | uart\_sig\_9\_sel=6 | UART1\_TXD | UART 1 Transmit Data | | 36 | VDDIO\_2 | DI/DO | GPIO\_21 | 7 | uart\_sig\_9\_sel=7 | UART1\_RXD | UART 1 Receive Data | | 36 | VDDIO\_2 | DI/DO | GPIO\_21 | 7 | uart\_sig\_9\_sel=8 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 36 | VDDIO\_2 | DI/DO | GPIO\_21 | 7 | uart\_sig\_9\_sel=9 | - | - | | 36 | VDDIO\_2 | DI/DO | GPIO\_21 | 7 | uart\_sig\_9\_sel=10 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 36 | VDDIO\_2 | DI/DO | GPIO\_21 | 7 | uart\_sig\_9\_sel=11 | ISO11898\_RXD | CAN (ISO 11898) Receive Data | | 36 | VDDIO\_2 | DI/DO | GPIO\_21 | 8 | - | - | - | | 36 | VDDIO\_2 | DI/DO | GPIO\_21 | 9 | - | - | - | | 36 | VDDIO\_2 | DI/DO | GPIO\_21 | 10 | - | - | - | | 36 | VDDIO\_2 | DI/DO | GPIO\_21 | 11 | - | SWGPIO21 | Software GPIO 21 | | 36 | VDDIO\_2 | DI/DO | GPIO\_21 | 12 | - | - | - | | 36 | VDDIO\_2 | DI/DO | GPIO\_21 | 16 | reg\_pwm1\_io\_sel=0 | PWM0\_CH1P | PWM 0 Channel 1 Positive | | 36 | VDDIO\_2 | DI/DO | GPIO\_21 | 16 | reg\_pwm1\_io\_sel=1 | PWM0\_CH2N | PWM 0 Channel 2 Negative | | 36 | VDDIO\_2 | DI/DO | GPIO\_21 | 22 | - | - | - | | 36 | VDDIO\_2 | DI/DO | GPIO\_21 | 23 | - | - | - | | 36 | VDDIO\_2 | DI/DO | GPIO\_21 | 24 | - | - | - | | 36 | VDDIO\_2 | DI/DO | GPIO\_21 | 25 | - | - | - | | 36 | VDDIO\_2 | DI/DO | GPIO\_21 | 26 | - | M0\_JTAG\_TCK | M0 JTAG Test Clock | | 37 | VDDIO\_2 | DI/DO | GPIO\_22 | 0 | - | - | - | | 37 | VDDIO\_2 | DI/DO | GPIO\_22 | 1 | - | SPI\_MISO | SPI Master Input, Slave Output | | 37 | VDDIO\_2 | DI/DO | GPIO\_22 | 2 | - | - | | | 37 | VDDIO\_2 | DI/DO | GPIO\_22 | 3 | - | I2S\_DI/I2S\_RCLK\_O | I^2^S Data Input/I^2^S Receive Clock Output | | 37 | VDDIO\_2 | DI/DO | GPIO\_22 | 4 | - | - | - | | 37 | VDDIO\_2 | DI/DO | GPIO\_22 | 5 | - | I2C0\_SCL | I^2^C 0 Serial Clock | | 37 | VDDIO\_2 | DI/DO | GPIO\_22 | 6 | - | I2C1\_SCL | I^2^C 1 Serial Clock | | 37 | VDDIO\_2 | DI/DO | GPIO\_22 | 7 | uart\_sig\_10\_sel=0 | UART0\_RTS | UART 0 Request To Send | | 37 | VDDIO\_2 | DI/DO | GPIO\_22 | 7 | uart\_sig\_10\_sel=1 | UART0\_CTS | UART 0 Clear To Send | | 37 | VDDIO\_2 | DI/DO | GPIO\_22 | 7 | uart\_sig\_10\_sel=2 | UART0\_TXD | UART 0 Transmit Data | | 37 | VDDIO\_2 | DI/DO | GPIO\_22 | 7 | uart\_sig\_10\_sel=3 | UART0\_RXD | UART 0 Receive Data | | 37 | VDDIO\_2 | DI/DO | GPIO\_22 | 7 | uart\_sig\_10\_sel=4 | UART1\_RTS | UART 1 Request To Send | | 37 | VDDIO\_2 | DI/DO | GPIO\_22 | 7 | uart\_sig\_10\_sel=5 | UART1\_CTS | UART 1 Clear To Send | | 37 | VDDIO\_2 | DI/DO | GPIO\_22 | 7 | uart\_sig\_10\_sel=6 | UART1\_TXD | UART 1 Transmit Data | | 37 | VDDIO\_2 | DI/DO | GPIO\_22 | 7 | uart\_sig\_10\_sel=7 | UART1\_RXD | UART 1 Receive Data | | 37 | VDDIO\_2 | DI/DO | GPIO\_22 | 7 | uart\_sig\_10\_sel=8 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 37 | VDDIO\_2 | DI/DO | GPIO\_22 | 7 | uart\_sig\_10\_sel=9 | - | - | | 37 | VDDIO\_2 | DI/DO | GPIO\_22 | 7 | uart\_sig\_10\_sel=10 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 37 | VDDIO\_2 | DI/DO | GPIO\_22 | 7 | uart\_sig\_10\_sel=11 | ISO11898\_RXD | CAN (ISO 11898) Receive Data | | 37 | VDDIO\_2 | DI/DO | GPIO\_22 | 8 | - | - | - | | 37 | VDDIO\_2 | DI/DO | GPIO\_22 | 9 | - | - | - | | 37 | VDDIO\_2 | DI/DO | GPIO\_22 | 10 | - | - | - | | 37 | VDDIO\_2 | DI/DO | GPIO\_22 | 11 | - | SWGPIO22 | Software GPIO 22 | | 37 | VDDIO\_2 | DI/DO | GPIO\_22 | 12 | - | - | - | | 37 | VDDIO\_2 | DI/DO | GPIO\_22 | 16 | reg\_pwm1\_io\_sel=0 | PWM0\_CH2P | PWM 0 Channel 2 Positive | | 37 | VDDIO\_2 | DI/DO | GPIO\_22 | 16 | reg\_pwm1\_io\_sel=1 | PWM0\_CH3P | PWM 0 Channel 3 Positive | | 37 | VDDIO\_2 | DI/DO | GPIO\_22 | 22 | - | - | - | | 37 | VDDIO\_2 | DI/DO | GPIO\_22 | 23 | - | - | - | | 37 | VDDIO\_2 | DI/DO | GPIO\_22 | 24 | - | - | - | | 37 | VDDIO\_2 | DI/DO | GPIO\_22 | 25 | - | AUDAC\_PWM\_P | AUDAC\_PWM\_P | | 37 | VDDIO\_2 | DI/DO | GPIO\_22 | 26 | - | M0\_JTAG\_TDO | M0 JTAG Test Data Out | | 38 | VDDIO\_2 | DI/DO | GPIO\_23 | 0 | - | - | - | | 38 | VDDIO\_2 | DI/DO | GPIO\_23 | 1 | - | SPI\_MOSI | SPI Master Output, Slave Input | | 38 | VDDIO\_2 | DI/DO | GPIO\_23 | 2 | - | - | - | | 38 | VDDIO\_2 | DI/DO | GPIO\_23 | 3 | - | I2S\_DO/I2S\_RCLK\_O | I^2^S Data Output/I^2^S Receive Clock
Output | | 38 | VDDIO\_2 | DI/DO | GPIO\_23 | 4 | - | - | - | | 38 | VDDIO\_2 | DI/DO | GPIO\_23 | 5 | - | I2C0\_SDA | I^2^C 0 Serial Data | | 38 | VDDIO\_2 | DI/DO | GPIO\_23 | 6 | - | I2C1\_SDA | I^2^C 1 Serial Data | | 38 | VDDIO\_2 | DI/DO | GPIO\_23 | 7 | uart\_sig\_11\_sel=0 | UART0\_RTS | UART 0 Request To Send | | 38 | VDDIO\_2 | DI/DO | GPIO\_23 | 7 | uart\_sig\_11\_sel=1 | UART0\_CTS | UART 0 Clear To Send | | 38 | VDDIO\_2 | DI/DO | GPIO\_23 | 7 | uart\_sig\_11\_sel=2 | UART0\_TXD | UART 0 Transmit Data | | 38 | VDDIO\_2 | DI/DO | GPIO\_23 | 7 | uart\_sig\_11\_sel=3 | UART0\_RXD | UART 0 Receive Data | | 38 | VDDIO\_2 | DI/DO | GPIO\_23 | 7 | uart\_sig\_11\_sel=4 | UART1\_RTS | UART 1 Request To Send | | 38 | VDDIO\_2 | DI/DO | GPIO\_23 | 7 | uart\_sig\_11\_sel=5 | UART1\_CTS | UART 1 Clear To Send | | 38 | VDDIO\_2 | DI/DO | GPIO\_23 | 7 | uart\_sig\_11\_sel=6 | UART1\_TXD | UART 1 Transmit Data | | 38 | VDDIO\_2 | DI/DO | GPIO\_23 | 7 | uart\_sig\_11\_sel=7 | UART1\_RXD | UART 1 Receive Data | | 38 | VDDIO\_2 | DI/DO | GPIO\_23 | 7 | uart\_sig\_11\_sel=8 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 38 | VDDIO\_2 | DI/DO | GPIO\_23 | 7 | uart\_sig\_11\_sel=9 | - | - | | 38 | VDDIO\_2 | DI/DO | GPIO\_23 | 7 | uart\_sig\_11\_sel=10 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 38 | VDDIO\_2 | DI/DO | GPIO\_23 | 7 | uart\_sig\_11\_sel=11 | ISO11898\_RXD | CAN (ISO 11898) Receive Data | | 38 | VDDIO\_2 | DI/DO | GPIO\_23 | 8 | - | - | - | | 38 | VDDIO\_2 | DI/DO | GPIO\_23 | 9 | - | - | - | | 38 | VDDIO\_2 | DI/DO | GPIO\_23 | 10 | - | AUADC\_CH3 | Audio ADC Channel 3 | | 38 | VDDIO\_2 | DI/DO | GPIO\_23 | 11 | - | SWGPIO23 | Software GPIO 23 | | 38 | VDDIO\_2 | DI/DO | GPIO\_23 | 12 | - | - | - | | 38 | VDDIO\_2 | DI/DO | GPIO\_23 | 16 | reg\_pwm1\_io\_sel=0 | PWM0\_CH3P | PWM 0 Channel 3 Positive | | 38 | VDDIO\_2 | DI/DO | GPIO\_23 | 16 | reg\_pwm1\_io\_sel=1 | PWM0\_CH3N | PWM 0 Channel 3 Negative | | 38 | VDDIO\_2 | DI/DO | GPIO\_23 | 22 | - | - | - | | 38 | VDDIO\_2 | DI/DO | GPIO\_23 | 23 | - | - | - | | 38 | VDDIO\_2 | DI/DO | GPIO\_23 | 24 | - | - | - | | 38 | VDDIO\_2 | DI/DO | GPIO\_23 | 25 | - | AUDAC\_PWM\_N | AUDAC\_PWM\_N | | 38 | VDDIO\_2 | DI/DO | GPIO\_23 | 26 | - | M0\_JTAG\_TDI | M0 JTAG Test Data Input | | 39 | VDDIO\_2 | DI/DO | GPIO\_24 | 0 | - | - | - | | 39 | VDDIO\_2 | DI/DO | GPIO\_24 | 1 | - | SPI\_SS | SPI Slave Select | | 39 | VDDIO\_2 | DI/DO | GPIO\_24 | 2 | - | - | - | | 39 | VDDIO\_2 | DI/DO | GPIO\_24 | 3 | - | I2S\_BCLK | I^2^S Bit Clock | | 39 | VDDIO\_2 | DI/DO | GPIO\_24 | 4 | - | - | - | | 39 | VDDIO\_2 | DI/DO | GPIO\_24 | 5 | - | I2C0\_SCL | I^2^C 0 Serial Clock | | 39 | VDDIO\_2 | DI/DO | GPIO\_24 | 6 | - | I2C1\_SCL | I^2^C 1 Serial Clock | | 39 | VDDIO\_2 | DI/DO | GPIO\_24 | 7 | uart\_sig\_0\_sel=0 | UART0\_RTS | UART 0 Request To Send | | 39 | VDDIO\_2 | DI/DO | GPIO\_24 | 7 | uart\_sig\_0\_sel=1 | UART0\_CTS | UART 0 Clear To Send | | 39 | VDDIO\_2 | DI/DO | GPIO\_24 | 7 | uart\_sig\_0\_sel=2 | UART0\_TXD | UART 0 Transmit Data | | 39 | VDDIO\_2 | DI/DO | GPIO\_24 | 7 | uart\_sig\_0\_sel=3 | UART0\_RXD | UART 0 Receive Data | | 39 | VDDIO\_2 | DI/DO | GPIO\_24 | 7 | uart\_sig\_0\_sel=4 | UART1\_RTS | UART 1 Request To Send | | 39 | VDDIO\_2 | DI/DO | GPIO\_24 | 7 | uart\_sig\_0\_sel=5 | UART1\_CTS | UART 1 Clear To Send | | 39 | VDDIO\_2 | DI/DO | GPIO\_24 | 7 | uart\_sig\_0\_sel=6 | UART1\_TXD | UART 1 Transmit Data | | 39 | VDDIO\_2 | DI/DO | GPIO\_24 | 7 | uart\_sig\_0\_sel=7 | UART1\_RXD | UART 1 Receive Data | | 39 | VDDIO\_2 | DI/DO | GPIO\_24 | 7 | uart\_sig\_0\_sel=8 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 39 | VDDIO\_2 | DI/DO | GPIO\_24 | 7 | uart\_sig\_0\_sel=9 | - | - | | 39 | VDDIO\_2 | DI/DO | GPIO\_24 | 7 | uart\_sig\_0\_sel=10 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 39 | VDDIO\_2 | DI/DO | GPIO\_24 | 7 | uart\_sig\_0\_sel=11 | ISO11898\_RXD | CAN (ISO 11898) Receive Data | | 39 | VDDIO\_2 | DI/DO | GPIO\_24 | 8 | - | - | - | | 39 | VDDIO\_2 | DI/DO | GPIO\_24 | 9 | - | CAM0\_DAT0 | Camera 0 Data 0 | | 39 | VDDIO\_2 | DI/DO | GPIO\_24 | 10 | - | - | - | | 39 | VDDIO\_2 | DI/DO | GPIO\_24 | 11 | - | SWGPIO24 | Software GPIO 24 | | 39 | VDDIO\_2 | DI/DO | GPIO\_24 | 12 | - | - | - | | 39 | VDDIO\_2 | DI/DO | GPIO\_24 | 16 | reg\_pwm1\_io\_sel=0 | PWM0\_CH0P | PWM 0 Channel 0 Positive | | 39 | VDDIO\_2 | DI/DO | GPIO\_24 | 16 | reg\_pwm1\_io\_sel=1 | PWM0\_CH0P | PWM 0 Channel 0 Positive | | 39 | VDDIO\_2 | DI/DO | GPIO\_24 | 22 | - | - | - | | 39 | VDDIO\_2 | DI/DO | GPIO\_24 | 23 | - | - | - | | 39 | VDDIO\_2 | DI/DO | GPIO\_24 | 24 | - | - | - | | 39 | VDDIO\_2 | DI/DO | GPIO\_24 | 25 | - | - | - | | 39 | VDDIO\_2 | DI/DO | GPIO\_24 | 26 | - | M0\_JTAG\_TMS | M0 JTAG Test Mode Select | | 40 | VDDIO\_2 | DI/DO | GPIO\_25 | 0 | - | - | - | | 40 | VDDIO\_2 | DI/DO | GPIO\_25 | 1 | - | SPI\_SCLK | SPI Serial Clock | | 40 | VDDIO\_2 | DI/DO | GPIO\_25 | 2 | - | - | - | | 40 | VDDIO\_2 | DI/DO | GPIO\_25 | 3 | - | I2S\_FS | I^2^S Frame Sync | | 40 | VDDIO\_2 | DI/DO | GPIO\_25 | 4 | - | PDM\_0\_IN | PDM Data Line | | 40 | VDDIO\_2 | DI/DO | GPIO\_25 | 5 | - | I2C0\_SDA | I^2^C 0 Serial Data | | 40 | VDDIO\_2 | DI/DO | GPIO\_25 | 6 | - | I2C1\_SDA | I^2^C 1 Serial Data | | 40 | VDDIO\_2 | DI/DO | GPIO\_25 | 7 | uart\_sig\_1\_sel=0 | UART0\_RTS | UART 0 Request To Send | | 40 | VDDIO\_2 | DI/DO | GPIO\_25 | 7 | uart\_sig\_1\_sel=1 | UART0\_CTS | UART 0 Clear To Send | | 40 | VDDIO\_2 | DI/DO | GPIO\_25 | 7 | uart\_sig\_1\_sel=2 | UART0\_TXD | UART 0 Transmit Data | | 40 | VDDIO\_2 | DI/DO | GPIO\_25 | 7 | uart\_sig\_1\_sel=3 | UART0\_RXD | UART 0 Receive Data | | 40 | VDDIO\_2 | DI/DO | GPIO\_25 | 7 | uart\_sig\_1\_sel=4 | UART1\_RTS | UART 1 Request To Send | | 40 | VDDIO\_2 | DI/DO | GPIO\_25 | 7 | uart\_sig\_1\_sel=5 | UART1\_CTS | UART 1 Clear To Send | | 40 | VDDIO\_2 | DI/DO | GPIO\_25 | 7 | uart\_sig\_1\_sel=6 | UART1\_TXD | UART 1 Transmit Data | | 40 | VDDIO\_2 | DI/DO | GPIO\_25 | 7 | uart\_sig\_1\_sel=7 | UART1\_RXD | UART 1 Receive Data | | 40 | VDDIO\_2 | DI/DO | GPIO\_25 | 7 | uart\_sig\_1\_sel=8 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 40 | VDDIO\_2 | DI/DO | GPIO\_25 | 7 | uart\_sig\_1\_sel=9 | - | - | | 40 | VDDIO\_2 | DI/DO | GPIO\_25 | 7 | uart\_sig\_1\_sel=10 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 40 | VDDIO\_2 | DI/DO | GPIO\_25 | 7 | uart\_sig\_1\_sel=11 | ISO11898\_RXD | CAN (ISO 11898) Receive Data | | 40 | VDDIO\_2 | DI/DO | GPIO\_25 | 8 | - | RMII\_REF\_CLK | RMII Reference Clock | | 40 | VDDIO\_2 | DI/DO | GPIO\_25 | 9 | - | CAM0\_DAT1 | Camera 0 Data 1 | | 40 | VDDIO\_2 | DI/DO | GPIO\_25 | 10 | - | - | - | | 40 | VDDIO\_2 | DI/DO | GPIO\_25 | 11 | - | SWGPIO25 | Software GPIO 25 | | 40 | VDDIO\_2 | DI/DO | GPIO\_25 | 12 | - | - | - | | 40 | VDDIO\_2 | DI/DO | GPIO\_25 | 16 | reg\_pwm1\_io\_sel=0 | PWM0\_CH1P | PWM 0 Channel 1 Positive | | 40 | VDDIO\_2 | DI/DO | GPIO\_25 | 16 | reg\_pwm1\_io\_sel=1 | PWM0\_CH0N | PWM 0 Channel 0 Negative | | 40 | VDDIO\_2 | DI/DO | GPIO\_25 | 22 | - | - | - | | 40 | VDDIO\_2 | DI/DO | GPIO\_25 | 23 | - | - | - | | 40 | VDDIO\_2 | DI/DO | GPIO\_25 | 24 | - | - | - | | 40 | VDDIO\_2 | DI/DO | GPIO\_25 | 25 | - | - | - | | 40 | VDDIO\_2 | DI/DO | GPIO\_25 | 26 | - | M0\_JTAG\_TCK | M0 JTAG Test Clock | | 41 | VDDIO\_2 | DI/DO | GPIO\_26 | 0 | - | - | - | | 41 | VDDIO\_2 | DI/DO | GPIO\_26 | 1 | - | SPI\_MISO | SPI Master Input, Slave Output | | 41 | VDDIO\_2 | DI/DO | GPIO\_26 | 2 | - | - | | | 41 | VDDIO\_2 | DI/DO | GPIO\_26 | 3 | - | I2S\_DI/I2S\_RCLK\_O | I^2^S Data Input/I^2^S Receive Clock Output | | 41 | VDDIO\_2 | DI/DO | GPIO\_26 | 4 | - | PDM\_CLK\_O | PDM Clock Line | | 41 | VDDIO\_2 | DI/DO | GPIO\_26 | 5 | - | I2C0\_SCL | I^2^C 0 Serial Clock | | 41 | VDDIO\_2 | DI/DO | GPIO\_26 | 6 | - | I2C1\_SCL | I^2^C 1 Serial Clock | | 41 | VDDIO\_2 | DI/DO | GPIO\_26 | 7 | uart\_sig\_2\_sel=0 | UART0\_RTS | UART 0 Request To Send | | 41 | VDDIO\_2 | DI/DO | GPIO\_26 | 7 | uart\_sig\_2\_sel=1 | UART0\_CTS | UART 0 Clear To Send | | 41 | VDDIO\_2 | DI/DO | GPIO\_26 | 7 | uart\_sig\_2\_sel=2 | UART0\_TXD | UART 0 Transmit Data | | 41 | VDDIO\_2 | DI/DO | GPIO\_26 | 7 | uart\_sig\_2\_sel=3 | UART0\_RXD | UART 0 Receive Data | | 41 | VDDIO\_2 | DI/DO | GPIO\_26 | 7 | uart\_sig\_2\_sel=4 | UART1\_RTS | UART 1 Request To Send | | 41 | VDDIO\_2 | DI/DO | GPIO\_26 | 7 | uart\_sig\_2\_sel=5 | UART1\_CTS | UART 1 Clear To Send | | 41 | VDDIO\_2 | DI/DO | GPIO\_26 | 7 | uart\_sig\_2\_sel=6 | UART1\_TXD | UART 1 Transmit Data | | 41 | VDDIO\_2 | DI/DO | GPIO\_26 | 7 | uart\_sig\_2\_sel=7 | UART1\_RXD | UART 1 Receive Data | | 41 | VDDIO\_2 | DI/DO | GPIO\_26 | 7 | uart\_sig\_2\_sel=8 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 41 | VDDIO\_2 | DI/DO | GPIO\_26 | 7 | uart\_sig\_2\_sel=9 | - | - | | 41 | VDDIO\_2 | DI/DO | GPIO\_26 | 7 | uart\_sig\_2\_sel=10 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 41 | VDDIO\_2 | DI/DO | GPIO\_26 | 7 | uart\_sig\_2\_sel=11 | ISO11898\_RXD | CAN (ISO 11898) Receive Data | | 41 | VDDIO\_2 | DI/DO | GPIO\_26 | 8 | - | RMII\_TXD[0] | RMII Transmit Data [0] | | 41 | VDDIO\_2 | DI/DO | GPIO\_26 | 9 | - | CAM0\_DAT2 | Camera 0 Data 2 | | 41 | VDDIO\_2 | DI/DO | GPIO\_26 | 10 | - | - | - | | 41 | VDDIO\_2 | DI/DO | GPIO\_26 | 11 | - | SWGPIO26 | Software GPIO 26 | | 41 | VDDIO\_2 | DI/DO | GPIO\_26 | 12 | - | - | - | | 41 | VDDIO\_2 | DI/DO | GPIO\_26 | 16 | reg\_pwm1\_io\_sel=0 | PWM0\_CH2P | PWM 0 Channel 2 Positive | | 41 | VDDIO\_2 | DI/DO | GPIO\_26 | 16 | reg\_pwm1\_io\_sel=1 | PWM0\_CH1P | PWM 0 Channel 1 Positive | | 41 | VDDIO\_2 | DI/DO | GPIO\_26 | 22 | - | - | - | | 41 | VDDIO\_2 | DI/DO | GPIO\_26 | 23 | - | - | - | | 41 | VDDIO\_2 | DI/DO | GPIO\_26 | 24 | - | - | - | | 41 | VDDIO\_2 | DI/DO | GPIO\_26 | 25 | - | - | - | | 41 | VDDIO\_2 | DI/DO | GPIO\_26 | 26 | - | M0\_JTAG\_TDO | M0 JTAG Test Data Out | | 42 | - | Power, Input | VDDIO2 | - | - | VDDIO2 | 1.8 V/3.3 V power supply of GPIO20 - GPIO34 | | 43 | VDDIO\_2 | DI/DO | GPIO\_27 | 0 | - | - | - | | 43 | VDDIO\_2 | DI/DO | GPIO\_27 | 1 | - | SPI\_MOSI | SPI Master Output, Slave Input | | 43 | VDDIO\_2 | DI/DO | GPIO\_27 | 2 | - | - | - | | 43 | VDDIO\_2 | DI/DO | GPIO\_27 | 3 | - | I2S\_DO/I2S\_RCLK\_O | I^2^S Data Output/I^2^S Receive Clock
Output | | 43 | VDDIO\_2 | DI/DO | GPIO\_27 | 4 | - | - | - | | 43 | VDDIO\_2 | DI/DO | GPIO\_27 | 5 | - | I2C0\_SDA | I^2^C 0 Serial Data | | 43 | VDDIO\_2 | DI/DO | GPIO\_27 | 6 | - | I2C1\_SDA | I^2^C 1 Serial Data | | 43 | VDDIO\_2 | DI/DO | GPIO\_27 | 7 | uart\_sig\_3\_sel=0 | UART0\_RTS | UART 0 Request To Send | | 43 | VDDIO\_2 | DI/DO | GPIO\_27 | 7 | uart\_sig\_3\_sel=1 | UART0\_CTS | UART 0 Clear To Send | | 43 | VDDIO\_2 | DI/DO | GPIO\_27 | 7 | uart\_sig\_3\_sel=2 | UART0\_TXD | UART 0 Transmit Data | | 43 | VDDIO\_2 | DI/DO | GPIO\_27 | 7 | uart\_sig\_3\_sel=3 | UART0\_RXD | UART 0 Receive Data | | 43 | VDDIO\_2 | DI/DO | GPIO\_27 | 7 | uart\_sig\_3\_sel=4 | UART1\_RTS | UART 1 Request To Send | | 43 | VDDIO\_2 | DI/DO | GPIO\_27 | 7 | uart\_sig\_3\_sel=5 | UART1\_CTS | UART 1 Clear To Send | | 43 | VDDIO\_2 | DI/DO | GPIO\_27 | 7 | uart\_sig\_3\_sel=6 | UART1\_TXD | UART 1 Transmit Data | | 43 | VDDIO\_2 | DI/DO | GPIO\_27 | 7 | uart\_sig\_3\_sel=7 | UART1\_RXD | UART 1 Receive Data | | 43 | VDDIO\_2 | DI/DO | GPIO\_27 | 7 | uart\_sig\_3\_sel=8 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 43 | VDDIO\_2 | DI/DO | GPIO\_27 | 7 | uart\_sig\_3\_sel=9 | - | - | | 43 | VDDIO\_2 | DI/DO | GPIO\_27 | 7 | uart\_sig\_3\_sel=10 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 43 | VDDIO\_2 | DI/DO | GPIO\_27 | 7 | uart\_sig\_3\_sel=11 | ISO11898\_RXD | CAN (ISO 11898) Receive Data | | 43 | VDDIO\_2 | DI/DO | GPIO\_27 | 8 | - | RMII\_TXD[1] | RMII Transmit Data [1] | | 43 | VDDIO\_2 | DI/DO | GPIO\_27 | 9 | - | CAM0\_DAT3 | Camera 0 Data 3 | | 43 | VDDIO\_2 | DI/DO | GPIO\_27 | 10 | - | ADC\_CH10/AUADC\_CH4 | ADC Channel 10/Audio ADC Channel 4 | | 43 | VDDIO\_2 | DI/DO | GPIO\_27 | 11 | - | SWGPIO27 | Software GPIO 27 | | 43 | VDDIO\_2 | DI/DO | GPIO\_27 | 12 | - | - | - | | 43 | VDDIO\_2 | DI/DO | GPIO\_27 | 16 | reg\_pwm1\_io\_sel=0 | PWM0\_CH3P | PWM 0 Channel 3 Positive | | 43 | VDDIO\_2 | DI/DO | GPIO\_27 | 16 | reg\_pwm1\_io\_sel=1 | PWM0\_CH1N | PWM 0 Channel 1 Negative | | 43 | VDDIO\_2 | DI/DO | GPIO\_27 | 22 | - | - | - | | 43 | VDDIO\_2 | DI/DO | GPIO\_27 | 23 | - | - | - | | 43 | VDDIO\_2 | DI/DO | GPIO\_27 | 24 | - | - | - | | 43 | VDDIO\_2 | DI/DO | GPIO\_27 | 25 | - | AUDAC\_PWM\_N | AUDAC\_PWM\_N | | 43 | VDDIO\_2 | DI/DO | GPIO\_27 | 26 | - | M0\_JTAG\_TDI | M0 JTAG Test Data Input | | 44 | VDDIO\_2 | DI/DO | GPIO\_28 | 0 | - | - | - | | 44 | VDDIO\_2 | DI/DO | GPIO\_28 | 1 | - | SPI\_SS | SPI Slave Select | | 44 | VDDIO\_2 | DI/DO | GPIO\_28 | 2 | - | - | - | | 44 | VDDIO\_2 | DI/DO | GPIO\_28 | 3 | - | I2S\_BCLK | I^2^S Bit Clock | | 44 | VDDIO\_2 | DI/DO | GPIO\_28 | 4 | - | - | - | | 44 | VDDIO\_2 | DI/DO | GPIO\_28 | 5 | - | I2C0\_SCL | I^2^C 0 Serial Clock | | 44 | VDDIO\_2 | DI/DO | GPIO\_28 | 6 | - | I2C1\_SCL | I^2^C 1 Serial Clock | | 44 | VDDIO\_2 | DI/DO | GPIO\_28 | 7 | uart\_sig\_4\_sel=0 | UART0\_RTS | UART 0 Request To Send | | 44 | VDDIO\_2 | DI/DO | GPIO\_28 | 7 | uart\_sig\_4\_sel=1 | UART0\_CTS | UART 0 Clear To Send | | 44 | VDDIO\_2 | DI/DO | GPIO\_28 | 7 | uart\_sig\_4\_sel=2 | UART0\_TXD | UART 0 Transmit Data | | 44 | VDDIO\_2 | DI/DO | GPIO\_28 | 7 | uart\_sig\_4\_sel=3 | UART0\_RXD | UART 0 Receive Data | | 44 | VDDIO\_2 | DI/DO | GPIO\_28 | 7 | uart\_sig\_4\_sel=4 | UART1\_RTS | UART 1 Request To Send | | 44 | VDDIO\_2 | DI/DO | GPIO\_28 | 7 | uart\_sig\_4\_sel=5 | UART1\_CTS | UART 1 Clear To Send | | 44 | VDDIO\_2 | DI/DO | GPIO\_28 | 7 | uart\_sig\_4\_sel=6 | UART1\_TXD | UART 1 Transmit Data | | 44 | VDDIO\_2 | DI/DO | GPIO\_28 | 7 | uart\_sig\_4\_sel=7 | UART1\_RXD | UART 1 Receive Data | | 44 | VDDIO\_2 | DI/DO | GPIO\_28 | 7 | uart\_sig\_4\_sel=8 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 44 | VDDIO\_2 | DI/DO | GPIO\_28 | 7 | uart\_sig\_4\_sel=9 | - | - | | 44 | VDDIO\_2 | DI/DO | GPIO\_28 | 7 | uart\_sig\_4\_sel=10 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 44 | VDDIO\_2 | DI/DO | GPIO\_28 | 7 | uart\_sig\_4\_sel=11 | ISO11898\_RXD | CAN (ISO 11898) Receive Data | | 44 | VDDIO\_2 | DI/DO | GPIO\_28 | 8 | - | RMII\_RXD[0] | RMII Receive Data [0] | | 44 | VDDIO\_2 | DI/DO | GPIO\_28 | 9 | - | CAM0\_HSYNC | Camera 0 Horizontal Sync | | 44 | VDDIO\_2 | DI/DO | GPIO\_28 | 10 | - | - | - | | 44 | VDDIO\_2 | DI/DO | GPIO\_28 | 11 | - | SWGPIO28 | Software GPIO 28 | | 44 | VDDIO\_2 | DI/DO | GPIO\_28 | 12 | - | - | - | | 44 | VDDIO\_2 | DI/DO | GPIO\_28 | 16 | reg\_pwm1\_io\_sel=0 | PWM0\_CH0P | PWM 0 Channel 0 Positive | | 44 | VDDIO\_2 | DI/DO | GPIO\_28 | 16 | reg\_pwm1\_io\_sel=1 | PWM0\_CH2P | PWM 0 Channel 2 Positive | | 44 | VDDIO\_2 | DI/DO | GPIO\_28 | 22 | - | - | - | | 44 | VDDIO\_2 | DI/DO | GPIO\_28 | 23 | - | - | - | | 44 | VDDIO\_2 | DI/DO | GPIO\_28 | 24 | - | - | - | | 44 | VDDIO\_2 | DI/DO | GPIO\_28 | 25 | - | AUDAC\_PWM\_P | AUDAC\_PWM\_P | | 44 | VDDIO\_2 | DI/DO | GPIO\_28 | 26 | - | M0\_JTAG\_TMS | M0 JTAG Test Mode Select | | 45 | VDDIO\_2 | DI/DO | GPIO\_29 | 0 | - | - | - | | 45 | VDDIO\_2 | DI/DO | GPIO\_29 | 1 | - | SPI\_SCLK | SPI Serial Clock | | 45 | VDDIO\_2 | DI/DO | GPIO\_29 | 2 | - | - | - | | 45 | VDDIO\_2 | DI/DO | GPIO\_29 | 3 | - | I2S\_FS | I^2^S Frame Sync | | 45 | VDDIO\_2 | DI/DO | GPIO\_29 | 4 | - | - | - | | 45 | VDDIO\_2 | DI/DO | GPIO\_29 | 5 | - | I2C0\_SDA | I^2^C 0 Serial Data | | 45 | VDDIO\_2 | DI/DO | GPIO\_29 | 6 | - | I2C1\_SDA | I^2^C 1 Serial Data | | 45 | VDDIO\_2 | DI/DO | GPIO\_29 | 7 | uart\_sig\_5\_sel=0 | UART0\_RTS | UART 0 Request To Send | | 45 | VDDIO\_2 | DI/DO | GPIO\_29 | 7 | uart\_sig\_5\_sel=1 | UART0\_CTS | UART 0 Clear To Send | | 45 | VDDIO\_2 | DI/DO | GPIO\_29 | 7 | uart\_sig\_5\_sel=2 | UART0\_TXD | UART 0 Transmit Data | | 45 | VDDIO\_2 | DI/DO | GPIO\_29 | 7 | uart\_sig\_5\_sel=3 | UART0\_RXD | UART 0 Receive Data | | 45 | VDDIO\_2 | DI/DO | GPIO\_29 | 7 | uart\_sig\_5\_sel=4 | UART1\_RTS | UART 1 Request To Send | | 45 | VDDIO\_2 | DI/DO | GPIO\_29 | 7 | uart\_sig\_5\_sel=5 | UART1\_CTS | UART 1 Clear To Send | | 45 | VDDIO\_2 | DI/DO | GPIO\_29 | 7 | uart\_sig\_5\_sel=6 | UART1\_TXD | UART 1 Transmit Data | | 45 | VDDIO\_2 | DI/DO | GPIO\_29 | 7 | uart\_sig\_5\_sel=7 | UART1\_RXD | UART 1 Receive Data | | 45 | VDDIO\_2 | DI/DO | GPIO\_29 | 7 | uart\_sig\_5\_sel=8 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 45 | VDDIO\_2 | DI/DO | GPIO\_29 | 7 | uart\_sig\_5\_sel=9 | - | - | | 45 | VDDIO\_2 | DI/DO | GPIO\_29 | 7 | uart\_sig\_5\_sel=10 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 45 | VDDIO\_2 | DI/DO | GPIO\_29 | 7 | uart\_sig\_5\_sel=11 | ISO11898\_RXD | CAN (ISO 11898) Receive Data | | 45 | VDDIO\_2 | DI/DO | GPIO\_29 | 8 | - | RMII\_RXD[1] | RMII Receive Data [1] | | 45 | VDDIO\_2 | DI/DO | GPIO\_29 | 9 | - | CAM0\_VSYNC | Camera 0 Vertical Sync | | 45 | VDDIO\_2 | DI/DO | GPIO\_29 | 10 | - | - | - | | 45 | VDDIO\_2 | DI/DO | GPIO\_29 | 11 | - | SWGPIO29 | Software GPIO 29 | | 45 | VDDIO\_2 | DI/DO | GPIO\_29 | 12 | - | - | - | | 45 | VDDIO\_2 | DI/DO | GPIO\_29 | 16 | reg\_pwm1\_io\_sel=0 | PWM0\_CH1P | PWM 0 Channel 1 Positive | | 45 | VDDIO\_2 | DI/DO | GPIO\_29 | 16 | reg\_pwm1\_io\_sel=1 | PWM0\_CH2N | PWM 0 Channel 2 Negative | | 45 | VDDIO\_2 | DI/DO | GPIO\_29 | 22 | - | - | - | | 45 | VDDIO\_2 | DI/DO | GPIO\_29 | 23 | - | - | - | | 45 | VDDIO\_2 | DI/DO | GPIO\_29 | 24 | - | - | - | | 45 | VDDIO\_2 | DI/DO | GPIO\_29 | 25 | - | - | - | | 45 | VDDIO\_2 | DI/DO | GPIO\_29 | 26 | - | M0\_JTAG\_TCK | M0 JTAG Test Clock | | 46 | VDDIO\_2 | DI/DO | GPIO\_30 | 0 | - | - | - | | 46 | VDDIO\_2 | DI/DO | GPIO\_30 | 1 | - | SPI\_MISO | SPI Master Input, Slave Output | | 46 | VDDIO\_2 | DI/DO | GPIO\_30 | 2 | - | - | - | | 46 | VDDIO\_2 | DI/DO | GPIO\_30 | 3 | - | I2S\_DI/I2S\_RCLK\_O | I^2^S Data Input/I^2^S Receive Clock Output | | 46 | VDDIO\_2 | DI/DO | GPIO\_30 | 4 | - | - | - | | 46 | VDDIO\_2 | DI/DO | GPIO\_30 | 5 | - | I2C0\_SCL | I^2^C 0 Serial Clock | | 46 | VDDIO\_2 | DI/DO | GPIO\_30 | 6 | - | I2C1\_SCL | I^2^C 1 Serial Clock | | 46 | VDDIO\_2 | DI/DO | GPIO\_30 | 7 | uart\_sig\_6\_sel=0 | UART0\_RTS | UART 0 Request To Send | | 46 | VDDIO\_2 | DI/DO | GPIO\_30 | 7 | uart\_sig\_6\_sel=1 | UART0\_CTS | UART 0 Clear To Send | | 46 | VDDIO\_2 | DI/DO | GPIO\_30 | 7 | uart\_sig\_6\_sel=2 | UART0\_TXD | UART 0 Transmit Data | | 46 | VDDIO\_2 | DI/DO | GPIO\_30 | 7 | uart\_sig\_6\_sel=3 | UART0\_RXD | UART 0 Receive Data | | 46 | VDDIO\_2 | DI/DO | GPIO\_30 | 7 | uart\_sig\_6\_sel=4 | UART1\_RTS | UART 1 Request To Send | | 46 | VDDIO\_2 | DI/DO | GPIO\_30 | 7 | uart\_sig\_6\_sel=5 | UART1\_CTS | UART 1 Clear To Send | | 46 | VDDIO\_2 | DI/DO | GPIO\_30 | 7 | uart\_sig\_6\_sel=6 | UART1\_TXD | UART 1 Transmit Data | | 46 | VDDIO\_2 | DI/DO | GPIO\_30 | 7 | uart\_sig\_6\_sel=7 | UART1\_RXD | UART 1 Receive Data | | 46 | VDDIO\_2 | DI/DO | GPIO\_30 | 7 | uart\_sig\_6\_sel=8 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 46 | VDDIO\_2 | DI/DO | GPIO\_30 | 7 | uart\_sig\_6\_sel=9 | - | - | | 46 | VDDIO\_2 | DI/DO | GPIO\_30 | 7 | uart\_sig\_6\_sel=10 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 46 | VDDIO\_2 | DI/DO | GPIO\_30 | 7 | uart\_sig\_6\_sel=11 | ISO11898\_RXD | CAN (ISO 11898) Receive Data | | 46 | VDDIO\_2 | DI/DO | GPIO\_30 | 8 | - | RMII\_RXERR | RMII Receive Error | | 46 | VDDIO\_2 | DI/DO | GPIO\_30 | 9 | - | CAM0\_CLK | Camera 0 Clock | | 46 | VDDIO\_2 | DI/DO | GPIO\_30 | 10 | - | AUADC\_CH7 | Audio ADC Channel 7 | | 46 | VDDIO\_2 | DI/DO | GPIO\_30 | 11 | - | SWGPIO30 | Software GPIO 30 | | 46 | VDDIO\_2 | DI/DO | GPIO\_30 | 12 | - | - | - | | 46 | VDDIO\_2 | DI/DO | GPIO\_30 | 16 | reg\_pwm1\_io\_sel=0 | PWM0\_CH2P | PWM 0 Channel 2 Positive | | 46 | VDDIO\_2 | DI/DO | GPIO\_30 | 16 | reg\_pwm1\_io\_sel=1 | PWM0\_CH3P | PWM 0 Channel 3 Positive | | 46 | VDDIO\_2 | DI/DO | GPIO\_30 | 22 | - | - | - | | 46 | VDDIO\_2 | DI/DO | GPIO\_30 | 23 | - | - | - | | 46 | VDDIO\_2 | DI/DO | GPIO\_30 | 24 | - | - | - | | 46 | VDDIO\_2 | DI/DO | GPIO\_30 | 25 | - | - | - | | 46 | VDDIO\_2 | DI/DO | GPIO\_30 | 26 | - | M0\_JTAG\_TDO | M0 JTAG Test Data Out | | 47 | VDDIO\_2 | DI/DO | GPIO\_31 | 0 | - | - | - | | 47 | VDDIO\_2 | DI/DO | GPIO\_31 | 1 | - | SPI\_MOSI | SPI Master Output, Slave Input | | 47 | VDDIO\_2 | DI/DO | GPIO\_31 | 2 | - | - | - | | 47 | VDDIO\_2 | DI/DO | GPIO\_31 | 3 | - | I2S\_DO/I2S\_RCLK\_O | I^2^S Data Output/I^2^S Receive Clock
Output | | 47 | VDDIO\_2 | DI/DO | GPIO\_31 | 4 | - | - | - | | 47 | VDDIO\_2 | DI/DO | GPIO\_31 | 5 | - | I2C0\_SDA | I^2^C 0 Serial Data | | 47 | VDDIO\_2 | DI/DO | GPIO\_31 | 6 | - | I2C1\_SDA | I^2^C 1 Serial Data | | 47 | VDDIO\_2 | DI/DO | GPIO\_31 | 7 | uart\_sig\_7\_sel=0 | UART0\_RTS | UART 0 Request To Send | | 47 | VDDIO\_2 | DI/DO | GPIO\_31 | 7 | uart\_sig\_7\_sel=1 | UART0\_CTS | UART 0 Clear To Send | | 47 | VDDIO\_2 | DI/DO | GPIO\_31 | 7 | uart\_sig\_7\_sel=2 | UART0\_TXD | UART 0 Transmit Data | | 47 | VDDIO\_2 | DI/DO | GPIO\_31 | 7 | uart\_sig\_7\_sel=3 | UART0\_RXD | UART 0 Receive Data | | 47 | VDDIO\_2 | DI/DO | GPIO\_31 | 7 | uart\_sig\_7\_sel=4 | UART1\_RTS | UART 1 Request To Send | | 47 | VDDIO\_2 | DI/DO | GPIO\_31 | 7 | uart\_sig\_7\_sel=5 | UART1\_CTS | UART 1 Clear To Send | | 47 | VDDIO\_2 | DI/DO | GPIO\_31 | 7 | uart\_sig\_7\_sel=6 | UART1\_TXD | UART 1 Transmit Data | | 47 | VDDIO\_2 | DI/DO | GPIO\_31 | 7 | uart\_sig\_7\_sel=7 | UART1\_RXD | UART 1 Receive Data | | 47 | VDDIO\_2 | DI/DO | GPIO\_31 | 7 | uart\_sig\_7\_sel=8 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 47 | VDDIO\_2 | DI/DO | GPIO\_31 | 7 | uart\_sig\_7\_sel=9 | - | - | | 47 | VDDIO\_2 | DI/DO | GPIO\_31 | 7 | uart\_sig\_7\_sel=10 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 47 | VDDIO\_2 | DI/DO | GPIO\_31 | 7 | uart\_sig\_7\_sel=11 | ISO11898\_RXD | CAN (ISO 11898) Receive Data | | 47 | VDDIO\_2 | DI/DO | GPIO\_31 | 8 | - | RMII\_TX\_EN | RMII Transmit Enable | | 47 | VDDIO\_2 | DI/DO | GPIO\_31 | 9 | - | CAM0\_DAT4 | Camera 0 Data 4 | | 47 | VDDIO\_2 | DI/DO | GPIO\_31 | 10 | - | - | - | | 47 | VDDIO\_2 | DI/DO | GPIO\_31 | 11 | - | SWGPIO31 | Software GPIO 31 | | 47 | VDDIO\_2 | DI/DO | GPIO\_31 | 12 | - | - | - | | 47 | VDDIO\_2 | DI/DO | GPIO\_31 | 16 | reg\_pwm1\_io\_sel=0 | PWM0\_CH3P | PWM 0 Channel 3 Positive | | 47 | VDDIO\_2 | DI/DO | GPIO\_31 | 16 | reg\_pwm1\_io\_sel=1 | PWM0\_CH3N | PWM 0 Channel 3 Negative | | 47 | VDDIO\_2 | DI/DO | GPIO\_31 | 22 | - | - | - | | 47 | VDDIO\_2 | DI/DO | GPIO\_31 | 23 | - | - | - | | 47 | VDDIO\_2 | DI/DO | GPIO\_31 | 24 | - | - | - | | 47 | VDDIO\_2 | DI/DO | GPIO\_31 | 25 | - | - | - | | 47 | VDDIO\_2 | DI/DO | GPIO\_31 | 26 | - | M0\_JTAG\_TDI | M0 JTAG Test Data Input | | 48 | VDDIO\_2 | DI/DO | GPIO\_32 | 0 | - | - | - | | 48 | VDDIO\_2 | DI/DO | GPIO\_32 | 1 | - | SPI\_SS | SPI Slave Select | | 48 | VDDIO\_2 | DI/DO | GPIO\_32 | 2 | - | - | - | | 48 | VDDIO\_2 | DI/DO | GPIO\_32 | 3 | - | I2S\_BCLK | I^2^S Bit Clock | | 48 | VDDIO\_2 | DI/DO | GPIO\_32 | 4 | - | - | - | | 48 | VDDIO\_2 | DI/DO | GPIO\_32 | 5 | - | I2C0\_SCL | I^2^C 0 Serial Clock | | 48 | VDDIO\_2 | DI/DO | GPIO\_32 | 6 | - | I2C1\_SCL | I^2^C 1 Serial Clock | | 48 | VDDIO\_2 | DI/DO | GPIO\_32 | 7 | uart\_sig\_8\_sel=0 | UART0\_RTS | UART 0 Request To Send | | 48 | VDDIO\_2 | DI/DO | GPIO\_32 | 7 | uart\_sig\_8\_sel=1 | UART0\_CTS | UART 0 Clear To Send | | 48 | VDDIO\_2 | DI/DO | GPIO\_32 | 7 | uart\_sig\_8\_sel=2 | UART0\_TXD | UART 0 Transmit Data | | 48 | VDDIO\_2 | DI/DO | GPIO\_32 | 7 | uart\_sig\_8\_sel=3 | UART0\_RXD | UART 0 Receive Data | | 48 | VDDIO\_2 | DI/DO | GPIO\_32 | 7 | uart\_sig\_8\_sel=4 | UART1\_RTS | UART 1 Request To Send | | 48 | VDDIO\_2 | DI/DO | GPIO\_32 | 7 | uart\_sig\_8\_sel=5 | UART1\_CTS | UART 1 Clear To Send | | 48 | VDDIO\_2 | DI/DO | GPIO\_32 | 7 | uart\_sig\_8\_sel=6 | UART1\_TXD | UART 1 Transmit Data | | 48 | VDDIO\_2 | DI/DO | GPIO\_32 | 7 | uart\_sig\_8\_sel=7 | UART1\_RXD | UART 1 Receive Data | | 48 | VDDIO\_2 | DI/DO | GPIO\_32 | 7 | uart\_sig\_8\_sel=8 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 48 | VDDIO\_2 | DI/DO | GPIO\_32 | 7 | uart\_sig\_8\_sel=9 | - | - | | 48 | VDDIO\_2 | DI/DO | GPIO\_32 | 7 | uart\_sig\_8\_sel=10 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 48 | VDDIO\_2 | DI/DO | GPIO\_32 | 7 | uart\_sig\_8\_sel=11 | ISO11898\_RXD | CAN (ISO 11898) Receive Data | | 48 | VDDIO\_2 | DI/DO | GPIO\_32 | 8 | - | RMII\_RX\_DV | RMII Receive Data Valid | | 48 | VDDIO\_2 | DI/DO | GPIO\_32 | 9 | - | CAM0\_DAT5 | Camera 0 Data 5 | | 48 | VDDIO\_2 | DI/DO | GPIO\_32 | 10 | - | - | - | | 48 | VDDIO\_2 | DI/DO | GPIO\_32 | 11 | - | SWGPIO32 | Software GPIO 32 | | 48 | VDDIO\_2 | DI/DO | GPIO\_32 | 12 | - | - | - | | 48 | VDDIO\_2 | DI/DO | GPIO\_32 | 16 | reg\_pwm1\_io\_sel=0 | PWM0\_CH0P | PWM 0 Channel 0 Positive | | 48 | VDDIO\_2 | DI/DO | GPIO\_32 | 16 | reg\_pwm1\_io\_sel=1 | PWM0\_CH0P | PWM 0 Channel 0 Positive | | 48 | VDDIO\_2 | DI/DO | GPIO\_32 | 22 | - | - | - | | 48 | VDDIO\_2 | DI/DO | GPIO\_32 | 23 | - | - | - | | 48 | VDDIO\_2 | DI/DO | GPIO\_32 | 24 | - | - | - | | 48 | VDDIO\_2 | DI/DO | GPIO\_32 | 25 | - | - | - | | 48 | VDDIO\_2 | DI/DO | GPIO\_32 | 26 | - | M0\_JTAG\_TMS | M0 JTAG Test Mode Select | | 49 | VDDIO\_2 | DI/DO | GPIO\_33 | 0 | - | - | - | | 49 | VDDIO\_2 | DI/DO | GPIO\_33 | 1 | - | SPI\_SCLK | SPI Serial Clock | | 49 | VDDIO\_2 | DI/DO | GPIO\_33 | 2 | - | - | - | | 49 | VDDIO\_2 | DI/DO | GPIO\_33 | 3 | - | I2S\_FS | I^2^S Frame Sync | | 49 | VDDIO\_2 | DI/DO | GPIO\_33 | 4 | - | - | - | | 49 | VDDIO\_2 | DI/DO | GPIO\_33 | 5 | - | I2C0\_SDA | I^2^C 0 Serial Data | | 49 | VDDIO\_2 | DI/DO | GPIO\_33 | 6 | - | I2C1\_SDA | I^2^C 1 Serial Data | | 49 | VDDIO\_2 | DI/DO | GPIO\_33 | 7 | uart\_sig\_9\_sel=0 | UART0\_RTS | UART 0 Request To Send | | 49 | VDDIO\_2 | DI/DO | GPIO\_33 | 7 | uart\_sig\_9\_sel=1 | UART0\_CTS | UART 0 Clear To Send | | 49 | VDDIO\_2 | DI/DO | GPIO\_33 | 7 | uart\_sig\_9\_sel=2 | UART0\_TXD | UART 0 Transmit Data | | 49 | VDDIO\_2 | DI/DO | GPIO\_33 | 7 | uart\_sig\_9\_sel=3 | UART0\_RXD | UART 0 Receive Data | | 49 | VDDIO\_2 | DI/DO | GPIO\_33 | 7 | uart\_sig\_9\_sel=4 | UART1\_RTS | UART 1 Request To Send | | 49 | VDDIO\_2 | DI/DO | GPIO\_33 | 7 | uart\_sig\_9\_sel=5 | UART1\_CTS | UART 1 Clear To Send | | 49 | VDDIO\_2 | DI/DO | GPIO\_33 | 7 | uart\_sig\_9\_sel=6 | UART1\_TXD | UART 1 Transmit Data | | 49 | VDDIO\_2 | DI/DO | GPIO\_33 | 7 | uart\_sig\_9\_sel=7 | UART1\_RXD | UART 1 Receive Data | | 49 | VDDIO\_2 | DI/DO | GPIO\_33 | 7 | uart\_sig\_9\_sel=8 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 49 | VDDIO\_2 | DI/DO | GPIO\_33 | 7 | uart\_sig\_9\_sel=9 | - | - | | 49 | VDDIO\_2 | DI/DO | GPIO\_33 | 7 | uart\_sig\_9\_sel=10 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 49 | VDDIO\_2 | DI/DO | GPIO\_33 | 7 | uart\_sig\_9\_sel=11 | ISO11898\_RXD | CAN (ISO 11898) Receive Data | | 49 | VDDIO\_2 | DI/DO | GPIO\_33 | 8 | - | RMII\_MDC | RMII Management Data Clock | | 49 | VDDIO\_2 | DI/DO | GPIO\_33 | 9 | - | CAM0\_DAT6 | Camera 0 Data 6 | | 49 | VDDIO\_2 | DI/DO | GPIO\_33 | 10 | - | - | - | | 49 | VDDIO\_2 | DI/DO | GPIO\_33 | 11 | - | SWGPIO33 | Software GPIO 33 | | 49 | VDDIO\_2 | DI/DO | GPIO\_33 | 12 | - | - | - | | 49 | VDDIO\_2 | DI/DO | GPIO\_33 | 16 | reg\_pwm1\_io\_sel=0 | PWM0\_CH1P | PWM 0 Channel 1 Positive | | 49 | VDDIO\_2 | DI/DO | GPIO\_33 | 16 | reg\_pwm1\_io\_sel=1 | PWM0\_CH0N | PWM 0 Channel 0 Negative | | 49 | VDDIO\_2 | DI/DO | GPIO\_33 | 22 | - | - | - | | 49 | VDDIO\_2 | DI/DO | GPIO\_33 | 23 | - | - | - | | 49 | VDDIO\_2 | DI/DO | GPIO\_33 | 24 | - | - | - | | 49 | VDDIO\_2 | DI/DO | GPIO\_33 | 25 | - | - | - | | 49 | VDDIO\_2 | DI/DO | GPIO\_33 | 26 | - | M0\_JTAG\_TCK | M0 JTAG Test Clock | | 50 | VDDIO\_2 | DI/DO | GPIO\_34 | 0 | - | - | - | | 50 | VDDIO\_2 | DI/DO | GPIO\_34 | 1 | - | SPI\_MISO | SPI Master Input, Slave Output | | 50 | VDDIO\_2 | DI/DO | GPIO\_34 | 2 | - | - | - | | 50 | VDDIO\_2 | DI/DO | GPIO\_34 | 3 | - | I2S\_DI/I2S\_RCLK\_O | I^2^S Data Input/I^2^S Receive Clock Output | | 50 | VDDIO\_2 | DI/DO | GPIO\_34 | 4 | - | - | - | | 50 | VDDIO\_2 | DI/DO | GPIO\_34 | 5 | - | I2C0\_SCL | I^2^C 0 Serial Clock | | 50 | VDDIO\_2 | DI/DO | GPIO\_34 | 6 | - | I2C1\_SCL | I^2^C 1 Serial Clock | | 50 | VDDIO\_2 | DI/DO | GPIO\_34 | 7 | uart\_sig\_10\_sel=0 | UART0\_RTS | UART 0 Request To Send | | 50 | VDDIO\_2 | DI/DO | GPIO\_34 | 7 | uart\_sig\_10\_sel=1 | UART0\_CTS | UART 0 Clear To Send | | 50 | VDDIO\_2 | DI/DO | GPIO\_34 | 7 | uart\_sig\_10\_sel=2 | UART0\_TXD | UART 0 Transmit Data | | 50 | VDDIO\_2 | DI/DO | GPIO\_34 | 7 | uart\_sig\_10\_sel=3 | UART0\_RXD | UART 0 Receive Data | | 50 | VDDIO\_2 | DI/DO | GPIO\_34 | 7 | uart\_sig\_10\_sel=4 | UART1\_RTS | UART 1 Request To Send | | 50 | VDDIO\_2 | DI/DO | GPIO\_34 | 7 | uart\_sig\_10\_sel=5 | UART1\_CTS | UART 1 Clear To Send | | 50 | VDDIO\_2 | DI/DO | GPIO\_34 | 7 | uart\_sig\_10\_sel=6 | UART1\_TXD | UART 1 Transmit Data | | 50 | VDDIO\_2 | DI/DO | GPIO\_34 | 7 | uart\_sig\_10\_sel=7 | UART1\_RXD | UART 1 Receive Data | | 50 | VDDIO\_2 | DI/DO | GPIO\_34 | 7 | uart\_sig\_10\_sel=8 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 50 | VDDIO\_2 | DI/DO | GPIO\_34 | 7 | uart\_sig\_10\_sel=9 | - | - | | 50 | VDDIO\_2 | DI/DO | GPIO\_34 | 7 | uart\_sig\_10\_sel=10 | ISO11898\_TXD | CAN (ISO 11898) Transmit Data | | 50 | VDDIO\_2 | DI/DO | GPIO\_34 | 7 | uart\_sig\_10\_sel=11 | ISO11898\_RXD | CAN (ISO 11898) Receive Data | | 50 | VDDIO\_2 | DI/DO | GPIO\_34 | 8 | - | RMII\_MDIO | RMII Management Data Input/Output | | 50 | VDDIO\_2 | DI/DO | GPIO\_34 | 9 | - | CAM0\_DAT7 | Camera 0 Data 7 | | 50 | VDDIO\_2 | DI/DO | GPIO\_34 | 10 | - | - | - | | 50 | VDDIO\_2 | DI/DO | GPIO\_34 | 11 | - | SWGPIO34 | Software GPIO 34 | | 50 | VDDIO\_2 | DI/DO | GPIO\_34 | 12 | - | - | - | | 50 | VDDIO\_2 | DI/DO | GPIO\_34 | 16 | reg\_pwm1\_io\_sel=0 | PWM0\_CH2P | PWM 0 Channel 2 Positive | | 50 | VDDIO\_2 | DI/DO | GPIO\_34 | 16 | reg\_pwm1\_io\_sel=1 | PWM0\_CH1P | PWM 0 Channel 1 Positive | | 50 | VDDIO\_2 | DI/DO | GPIO\_34 | 22 | - | - | - | | 50 | VDDIO\_2 | DI/DO | GPIO\_34 | 23 | - | - | - | | 50 | VDDIO\_2 | DI/DO | GPIO\_34 | 24 | - | - | - | | 50 | VDDIO\_2 | DI/DO | GPIO\_34 | 25 | - | - | - | | 50 | VDDIO\_2 | DI/DO | GPIO\_34 | 26 | - | M0\_JTAG\_TDO | M0 JTAG Test Data Out | | 51 | AVDD33\_RF3 | Clock | XTAL\_IN | - | - | XTAL\_IN | - | | 52 | AVDD33\_RF3 | Clock | XTAL\_OUT | - | - | XTAL\_OUT | - | | 53 | - | Power, Input | AVDD33\_RF3 | - | - | AVDD33\_RF3 | 3.3 V power supply of RF transceiver | | 54 | - | Power, Input | AVDD18\_RF | - | - | AVDD18\_RF | 1.8 V power supply of RF transceiver | | 55 | - | Power, Output | AVDD15\_RF2 | - | - | AVDD15\_RF2 | 1.5 V power supply of RF transceiver (internal regulator
output) | | 56 | - | Power, Input | AVDD15\_RF1 | - | - | AVDD15\_RF1 | 1.5 V power supply of RF transceiver | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Note: - Only one of CAM0 and CAM1 can be selected. - When selected as the SPI function, the default is SPI\_MISO, which can be converted to SPI\_MOSI through the register. ### Pin mux table Source: [https://docs.qualcomm.com/doc/80-WL748-1/topic/pin-definitions.html](https://docs.qualcomm.com/doc/80-WL748-1/topic/pin-definitions.html) | QCC748 | GPIO | Voltage | QSPI | Serial Flash | SDIO Slave | SDIO Master | SPI | I^2^C
0/1 | UART
0/1 | I^2^S | PWM | CAN (ISO11898) | Audio ADC | Audio DAC | EMAC | DVP | MIPI-DBI | JTAG | | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | | 4 | GPIO0 | VDDIO1 | - | - | - | - | CS | SCL | RTS/CTS/TX/RX | BCLK | CH0P/CH0P | TX/RX | CH9 | - | - | CAM1\_

VSYNC | - | TMS | | 5 | GPIO1 | VDDIO1 | - | - | - | - | CLK | SDA | RTS/CTS/TX/RX | FS | CH1P/CH0N | TX/RX | CH8 | - | - | CAM1\_

HSYNC | - | TCK | | 6 | GPIO2 | VDDIO1 | - | - | - | - | MISO | SCL | RTS/CTS/TX/RX | DI | CH2P/CH1P | TX/RX | CH2 | - | - | | - | TDO | | 7 | GPIO3 | VDDIO1 | - | - | - | - | MOSI | SDA | RTS/CTS/TX/RX | DO | CH3P/CH1N | TX/RX | CH3 | - | - | CAM1\_

DAT0 | - | TDI | | 8 | GPIO4 | VDDIO1 | SCL | SF2\_CS | - | - | CS | SCL | RTS/CTS/TX/RX | BCLK | CH0P/CH2P | TX/RX | - | - | - | | B\_WRn/C\_SCL | TMS | | 9 | GPIO5 | VDDIO1 | CS | SF2\_D1 | - | - | CLK | SDA | RTS/CTS/TX/RX | FS | CH1P/CH2N | TX/RX | - | - | - | - | B\_CSn/C\_CSn | TCK | | 10 | GPIO6 | VDDIO1 | SDA0 | SF2\_D2 | - | - | MISO | SCL | RTS/CTS/TX/RX | DI | CH2P/CH3P | TX/RX | - | - | - | - | B\_RDn/C\_SDA0 | TDO | | 11 | GPIO7 | VDDIO1 | SDA1 | SF2\_D0 | - | - | MOSI | SDA | RTS/CTS/TX/RX | DO | CH3P/CH3N | TX/RX | - | - | - | - | B\_DCn/C\_DCn | TDI | | 12 | GPIO8 | VDDIO1 | SDA2 | SF2\_CLK | - | - | CS | SCL | RTS/CTS/TX/RX | BCLK | CH0P/CH0P | TX/RX | - | - | - | - | B\_DB0/C\_SCL | TMS | | 14 | GPIO9 | VDDIO1 | SDA3 | SF2\_D3 | - | - | CLK | SDA | RTS/CTS/TX/RX | FS | CH1P/CH0N | TX/RX | - | - | - | - | B\_DB1/C\_CSn | TCK | | 15 | GPIO10 | VDDIO1 | SCL | SF3\_D3 | DAT2 | DAT1 | MISO | SCL | RTS/CTS/TX/RX | DI | CH2P/CH1P | TX/RX | CH7 | - | - | CAM1\_

DAT1 | B\_DB2/C\_SDA0 | TDO | | 16 | GPIO11 | VDDIO1 | CS | SF3\_CLK | DAT3 | DAT0 | MOSI | SDA | RTS/CTS/TX/RX | DO | CH3P/CH1N | TX/RX | - | - | - | CAM1\_

DAT2 | B\_DB3/C\_DCn | TDI | | 17 | GPIO12 | VDDIO1 | SDA0 | SF3\_D0 | CMD | CLK | CS | SCL | RTS/CTS/TX/RX | BCLK | CH0P/CH2P | TX/RX | CH6 | - | - | CAM1\_

DAT3 | B\_DB4/C\_SCL | TMS | | 18 | GPIO13 | VDDIO1 | SDA1 | SF3\_D2 | CLK | CMD | CLK | SDA | RTS/CTS/TX/RX | FS | CH1P/CH2N | TX/RX | CH5 | - | - | CAM1\_

CLK | B\_DB5/C\_CSn | TCK | | 19 | GPIO14 | VDDIO1 | SDA2 | SF3\_D1 | DAT0 | DAT3 | MISO | SCL | RTS/CTS/TX/RX | DI | CH2P/CH3P | TX/RX | CH4 | A\_PWM\_P | - | CAM1\_

DAT4 | B\_DB6/C\_SDA0 | TDO | | 20 | GPIO15 | VDDIO1 | SDA3 | SF3\_CS | DAT1 | DAT2 | MOSI | SDA | RTS/CTS/TX/RX | DO | CH3P/CH3N | TX/RX | - | A\_PWM\_N | - | CAM1\_

DAT5 | B\_DB7/C\_DCn | TDI | | 21 | GPIO16 | VDD33 | - | - | - | - | CS | SCL | RTS/CTS/TX/RX | BCLK | CH0P/CH0P | TX/RX | - | - | - | CAM1\_

DAT6 | - | TMS | | 22 | GPIO17 | VDD33 | - | - | - | - | CLK | SDA | RTS/CTS/TX/RX | FS | CH1P/CH0N | TX/RX | - | - | | CAM1\_

DAT7 | - | TCK | | 24 | GPIO19 | VDD33 | - | - | - | - | MOSI | SDA | RTS/CTS/TX/RX | DO | CH3P/CH1N | TX/RX | CH1 | - | - | - | - | TDI | | 35 | GPIO20 | VDDIO2 | - | - | - | - | CS | SCL | RTS/CTS/TX/RX | BCLK | CH0P/CH2P | TX/RX | CH0/A\_CH0 | - | - | - | - | TMS | | 36 | GPIO21 | VDDIO2 | - | - | - | - | CLK | SDA | RTS/CTS/TX/RX | FS | CH1P/CH2N | TX/RX | AU\_CH1 | - | - | - | - | TCK | | 37 | GPIO22 | VDDIO2 | - | - | - | - | MISO | SCL | RTS/CTS/TX/RX | DI | CH2P/CH3P | TX/RX | AU\_CH2 | A\_PWM\_P | - | - | - | TDO | | 38 | GPIO23 | VDDIO2 | - | - | - | - | MOSI | SDA | RTS/CTS/TX/RX | DO | CH3P/CH3N | TX/RX | AU\_CH3 | A\_PWM\_N | - | - | - | TDI | | 39 | GPIO24 | VDDIO2 | - | - | - | - | CS | SCL | RTS/CTS/TX/RX | BCLK | CH0P/CH0P | TX/RX | - | - | - | CAM0\_

DAT0 | - | TMS | | 40 | GPIO25 | VDDIO2 | - | - | - | - | CLK | SDA | RTS/CTS/TX/RX | FS | CH1P/CH0N | TX/RX | - | - | REF\_CLK | CAM0\_

DAT1 | - | TCK | | 41 | GPIO26 | VDDIO2 | - | - | - | - | MISO | SCL | RTS/CTS/TX/RX | DI | CH2P/CH1P | TX/RX | - | - | TXD[0] | CAM0\_

DAT2 | - | TDO | | 43 | GPIO27 | VDDIO2 | - | - | - | - | MOSI | SDA | RTS/CTS/TX/RX | DO | CH3P/CH1N | TX/RX | CH10/A\_CH4 | A\_PWM\_N | TXD[1] | CAM0\_

DAT3 | - | TDI | | 44 | GPIO28 | VDDIO2 | - | - | - | - | CS | SCL | RTS/CTS/TX/RX | BCLK | CH0P/CH2P | TX/RX | CH11/A\_CH5 | A\_PWM\_P | RXD[0] | CAM0\_

HSYNC | - | TMS | | 45 | GPIO29 | VDDIO2 | - | - | - | - | CLK | SDA | RTS/CTS/TX/RX | FS | CH1P/CH2N | TX/RX | AU\_CH6 | - | RXD[1] | CAM0\_

VSYNC | - | TCK | | 46 | GPIO30 | VDDIO2 | - | - | - | - | MISO | SCL | RTS/CTS/TX/RX | DI | CH2P/CH3P | TX/RX | AU\_CH7 | - | RXERR | CAM0\_

CLK | - | TDO | | 47 | GPIO31 | VDDIO2 | - | - | - | - | MOSI | SDA | RTS/CTS/TX/RX | DO | CH3P/CH3N | TX/RX | - | - | TX\_EN | CAM0\_

DAT4 | - | TDI | | 48 | GPIO32 | VDDIO2 | - | - | - | - | CS | SCL | RTS/CTS/TX/RX | BCLK | CH0P/CH0P | TX/RX | - | - | RX\_DV | CAM0\_

DAT5 | - | TMS | | 49 | GPIO33 | VDDIO2 | - | - | - | - | CLK | SDA | RTS/CTS/TX/RX | FS | CH1P/CH0N | TX/RX | - | - | MDC | CAM0\_

DAT6 | - | TCK | | 50 | GPIO34 | VDDIO2 | - | - | - | - | MISO | SCL | RTS/CTS/TX/RX | DI | CH2P/CH1P | TX/RX | - | - | MDIO | CAM0\_

DAT7 | - | TDO | Table : QCC748 GPIOs for external flash connection | Pin number | Pin name | Main function | Voltage domain | Type | Peripheral internal function select | Description | | --- | --- | --- | --- | --- | --- | --- | | 8 | GPIO\_4 | CS | VDDIO\_1 | DI/DO | Serial flash\_CS | Serial flash chip select | | 9 | GPIO\_5 | SO | VDDIO\_1 | DI/DO | Serial flash\_D1 | Serial flash Data 1 | | 10 | GPIO\_6 | WP | VDDIO\_1 | DI/DO | Serial flash\_D2 | Serial flash Data 2 | | 11 | GPIO\_7 | SI | VDDIO\_1 | DI/DO | Serial flash\_D0 | Serial flash Data 0 | | 12 | GPIO\_8 | SCLK | VDDIO\_1 | DI/DO | Serial flash\_CLK | Serial flash Clock | | 14 | GPIO\_9 | HOLD | VDDIO\_1 | DI/DO | Serial flash\_D3 | Serial flash Data 3 | Last Published: Apr 22, 2026 [Previous Topic Introduction](https://docs.qualcomm.com/bundle/publicresource/80-WL748-1/topics/introduction.md) [Next Topic Electrical specifications](https://docs.qualcomm.com/bundle/publicresource/80-WL748-1/topics/electrical-specifications.md)