# QCC730 system overview Source: [https://docs.qualcomm.com/doc/80-Y8730-2/topic/system_overview.html](https://docs.qualcomm.com/doc/80-Y8730-2/topic/system_overview.html) QCC730 is a micropower Wi‑Fi transceiver single package WLAN solution to support dual-band (2.4 GHz and 5 GHz) 1×1 802.11a/b/g/n WLAN standards. ## Processors Source: [https://docs.qualcomm.com/doc/80-Y8730-2/topic/system_overview.html](https://docs.qualcomm.com/doc/80-Y8730-2/topic/system_overview.html) QCC730 contains an Arm Cortex-M4F application processor, which runs lightweight Internet Protocol (lwIP) and Wi‑Fi dual‑band functions. The processor and memory subsystem attributes are as follows: - Arm Cortex-M4F at 60 MHz - Arm v7-M ISA (Thumb/Thumb-2) - Single-precision floating point - 640 KB static random access memory (SRAM): 256 KB available for customer code and data - 1447 KB resistive random access memory (RRAM) totally available for application image, which includes customer APP code and Qualcomm® software development kit (SDK) binary - Memory-mapped, cached view of external Quad Serial Peripheral Interface (QSPI) flash. The cache is specified as 32 KB with four-way associativity. QCC730 implements one dedicated 1x1 11n HT20 and up to MCS3 on-chip wireless subsystem. The following diagram illustrates the architecture of QCC730 software. ## Software architecture Source: [https://docs.qualcomm.com/doc/80-Y8730-2/topic/system_overview.html](https://docs.qualcomm.com/doc/80-Y8730-2/topic/system_overview.html) Figure : QCC730 software architecture overview Last Published: Jun 03, 2026 [Previous Topic About this document](https://docs.qualcomm.com/bundle/publicresource/80-Y8730-2/topics/introduction.md) [Next Topic Getting started](https://docs.qualcomm.com/bundle/publicresource/80-Y8730-2/topics/qcc730_application_development.md)