# Introduction
Source: [https://docs.qualcomm.com/doc/80-73480-1/topic/Introduction.html](https://docs.qualcomm.com/doc/80-73480-1/topic/Introduction.html)
This topic provides the detailed functional block diagram and the features of this
chipset.
## QCS615 functional block diagram
Source: [https://docs.qualcomm.com/doc/80-73480-1/topic/Introduction.html](https://docs.qualcomm.com/doc/80-73480-1/topic/Introduction.html)
The following functional block diagram shows the overall representation of the subsystems on
these chipsets.
## QCS615 features
Source: [https://docs.qualcomm.com/doc/80-73480-1/topic/Introduction.html](https://docs.qualcomm.com/doc/80-73480-1/topic/Introduction.html)
The following table lists the comprehensive features of the QCS615
chipset and its capabilities.
Some hardware features on the QCS615 are software-enabled. For details
of QCS615 software-enabled features, see the latest revision of the
applicable software release notes.
### Processor
| Feature | Description |
| --- | --- |
| CPU | Qualcomm® Kryo™ 460 – 64-bit application processor with a 1 MB L3 cache
Kryo Gold: Two high-performance cores running at 1.9 GHz with a 256 kB L2 cache per core
Kryo Silver: Six low-power cores running at 1.6 GHz with a 64 kB L2 cache per core
Error-correcting code (ECC) to support system-level use cases
|
| Digital signal processing (DSP) | Compute Hexagon DSP with dual Hexagon Vector eXtensions (HVX) for:
Object detection
Video playback enhancements
Virtual reality
Computer vision
Camera snapshot enhancements
Video capture enhancement
Deep learning
This DSP is a cache-based processor with full access to DDR memory |
| Always-on subsystem | Always-on subsystem with always-on processor.
The hardware-based resource and power management (RPMh) incorporates hardware accelerators for voltage control and regulation, clock management, and resource communication |
### Memory
| Feature | Description |
| --- | --- |
| System memory via EBI |
The memory offers a dual-channel high-speed LPDDR4X SDRAM
The LPDDR4X SDRAM optimizes a clock speed of 1555 MHz using a 2 × 16‑bit configuration
The system memory supports a 256 kB system cache
|
| External memory |
UFS 2.1 gear 3, one-lane for on-board memory
SD v3.0 4 bit for SD card and eMMC v5.1 8‑bit
Quad serial peripheral interface (QSPI): NOR flash
Qualcomm Spectra 230 supports Bayer RGB, YUV, RCCB, Mono, and it also features improved zzHDR
Three 4-lane MIPI CSI is configurable in 4 + 4 + 4 or 4 + 4 + 2 + 1 configuration
D-PHY v1.2: 2.5 Gbps/lane on 4 lanes per port, 10 Gbps/port, up to 30 Gbps total
C-PHY v1.0: 3.42 Gbps/trio on 3 trios per port, 10.2 Gbps/port, up to 30.6 Gbps total
|
| Video | Adreno video processing unit (VPU) 443 – fourth generation with support for ultra high definition (UHD)
Video decode up to 4K60
Video encode up to 4K30
Video concurrency of 4K30 decode and 1080p30 encode
Native decode support for H.265 main 10, H.265 main, H.264 high, VP9 profile 2, VP8, and MPEG-2 codecs
Native encode support for H.265 main, H.264 high, and VP8 codecs
|
| Graphics |
Adreno graphics processing unit (GPU) 612
OpenGL ES 3.2, Vulkan, and Vulkan compute, and DirectX 12 (DX12) feature level (FL) 9.3
OpenCL 2.0
|
| Audio | The hexagon digital signal processor (DSP) targets up to 1 GHz and with a 512 kB L2 cache
Qualcomm® Voice Activation
Echo cancellation and noise suppression (ECNS)
Qualcomm® Voice Suite, voice recognition, high fidelity playback, and surround sound
Qualcomm Voice Suite source tracking, sound focus, multi-channel echo cancellation, feedback cancellation, and support for up to two microphones
Voice codecs are:
EVRC, EVRC-B, and EVRC-WB
G.711 and G.729A/AB
GSM-FR, GSM-EFR, and GSM-HR
AMR-NB, AMR-WB, AMR-eAMR, and AMR-BeAMR
Audio codecs are:
MP3
AAC
HE AAC v1, v2
WMA 9/Pro
FLAC
APE
ALAC
AIFF
|
[^1^](https://docs.qualcomm.com/doc/80-73480-1/topic/Introduction.html#fnsrc_1_features) DisplayPort++ is not supported on QCS615.
### Physical interfaces
| Interface | Description |
| --- | --- |
| Qualcomm universal peripheral (QUP) ports | Qualcomm universal peripheral (QUP) ports provide the following multiplexed serial communication interfaces over eight GPIO based SEs and six SSC based SEs:
UART (4 MHz): available on GPIO QUP0/QUP2/QUP4/QUP7 SEs, and on all SSC QUPs
I²C master (1 MHz): available on GPIO QUP1/QUP2/QUP3/QUP4/QUP5/QUP7 SEs and for all SSC QUPs
SPI master (50 MHz): available on GPIO QUP2/QUP4/QUP6/QUP7 SEs and for all SSC QUPs
|
| CCI I²C master (1 MHz) | Two dedicated I²C interfaces for devices using CSI ports |
| Quad-SPI (65 MHz) | QSPI NOR flash external memory support (boot not supported) |
| USB |